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Searched refs:cycles (Results 1 – 25 of 67) sorted by relevance

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/openbmc/u-boot/cmd/
H A Dtime.c9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
29 ulong cycles = 0; in do_time() local
36 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
37 report_time(cycles); in do_time()
/openbmc/u-boot/arch/xtensa/lib/
H A Dtime.c24 static void delay_cycles(unsigned cycles) in delay_cycles() argument
27 unsigned expiry = get_ccount() + cycles; in delay_cycles()
39 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
41 fake_ccount += cycles; in delay_cycles()
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
H A Dkwbimage-memphis.cfg65 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
133 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
134 # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
136 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
141 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
143 # bit15-12: 1000, internal ODT de-assertion x cycles after write
H A Dkwbimage_128M16_1.cfg118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
197 # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
198 # (ODT turn off delay 2,5 clk cycles)
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg38 # bit4: 1, T2 mode, addr/cmd are driven for two cycles
139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
H A Dkwbimage-lschl.cfg139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/openbmc/qemu/docs/spin/
H A Dtcg-exclusive.promela45 # warning defaulting to 2 CPU cycles
48 # warning defaulting to 1 CPU cycles
185 byte cycles = 0;
189 :: cycles == N_CYCLES -> break;
191 cycles++;
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/openbmc/openbmc/meta-openembedded/meta-python/recipes-devtools/python/
H A Dpython3-cycler_0.12.1.bb1 SUMMARY = "Composable style cycles"
/openbmc/qemu/hw/timer/
H A Dnpcm7xx_timer.c165 int64_t cycles) in npcm7xx_watchdog_timer_reset_cycles() argument
167 int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); in npcm7xx_watchdog_timer_reset_cycles()
182 int64_t cycles = 1; in npcm7xx_watchdog_timer_reset() local
187 cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT; in npcm7xx_watchdog_timer_reset()
188 cycles <<= 2 * s; in npcm7xx_watchdog_timer_reset()
190 npcm7xx_watchdog_timer_reset_cycles(t, cycles); in npcm7xx_watchdog_timer_reset()
/openbmc/phosphor-post-code-manager/
H A Dmeson.options6 description: 'Maximum boot cycles for which the post codes should be persisted',
/openbmc/qemu/docs/
H A Dmulti-thread-compression.txt27 The process of compression will consume additional CPU cycles, and the
28 extra CPU cycles will increase the migration time. On the other hand,
48 Compression of data will consume extra CPU cycles; so in a system with
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg96 /* interleaved bank access (row/bank/col), 5 cycles additional read delay */
109 /* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */
/openbmc/qemu/hw/adc/
H A Dnpcm7xx_adc.c74 uint32_t cycles, uint32_t prescaler) in npcm7xx_adc_start_timer() argument
77 int64_t ticks = cycles; in npcm7xx_adc_start_timer()
/openbmc/u-boot/drivers/bootcount/
H A DKconfig104 int "Maximum number of reboot cycles allowed"
107 Set the Maximum number of reboot cycles allowed without the boot
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt25 …f the NIF is idle in Access state for auto-self-refresh-cnt * 32 * n_clk cycles.The automatic self…
26 …ed into power-down mode if the NIF is idle for auto-power-down-cnt n_clk cycles.The automatic powe…
/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig185 Enter a latency in number of cycles. This will be added to
195 Enter a latency in number of cycles. This will be added to
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_adc-test.c169 static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale, in adc_calculate_steps() argument
172 return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; in adc_calculate_steps()
/openbmc/qemu/target/arm/
H A Dcpregs-pmu.c89 static int64_t cycles_ns_per(uint64_t cycles) in cycles_ns_per() argument
91 return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; in cycles_ns_per()
131 static int64_t zero_event_ns_per(uint64_t cycles) in zero_event_ns_per() argument
481 uint64_t cycles = cycles_get_count(env); in pmccntr_op_start() local
484 uint64_t eff_cycles = cycles; in pmccntr_op_start()
500 env->cp15.c15_ccnt_delta = cycles; in pmccntr_op_start()
/openbmc/qemu/target/hexagon/imported/
H A Dsystem.idef34 "Enter low-power state for #u8 cycles",{fPAUSE(uiV);})
/openbmc/qemu/include/hw/xen/interface/
H A Dtrace.h279 } cycles; member
/openbmc/u-boot/arch/arm/dts/
H A Domap36xx.dtsi55 ti,clock-cycles = <8>;
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md59 LPC firmware cycles allow separate boot BIOS firmware memory cycles and
60 application memory cycles with respect to the LPC bus. The ASPEED BMCs allow
61 remapping of the LPC firmware cycles onto arbitrary regions of the BMC's
452 From the host side, the LPC Firmware and KCS IO cycles are driven by
/openbmc/phosphor-led-manager/
H A DREADME.md91 '_enclosure_identify_' group, with their respective states and duty cycles.

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