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Searched refs:cxl_root_port (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/tools/testing/cxl/test/
H A Dcxl.c29 static struct platform_device *cxl_root_port[NR_MULTI_ROOT]; variable
528 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) in is_mock_port()
529 if (dev == &cxl_root_port[i]->dev) in is_mock_port()
924 array_size = ARRAY_SIZE(cxl_root_port); in mock_cxl_port_enumerate_dports()
925 array = cxl_root_port; in mock_cxl_port_enumerate_dports()
1294 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) { in cxl_test_init()
1309 cxl_root_port[i] = pdev; in cxl_test_init()
1312 BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port)); in cxl_test_init()
1314 struct platform_device *root_port = cxl_root_port[i]; in cxl_test_init()
1403 for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--) in cxl_test_init()
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/openbmc/qemu/tests/qtest/
H A Dcxl-test.c102 static void cxl_root_port(void) in cxl_root_port() function
210 qtest_add_func("/pci/cxl/rp", cxl_root_port); in main()
/openbmc/qemu/hw/pci-bridge/
H A Dmeson.build10 pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c', 'cxl_upstream.c', 'cxl_downstream.…
/openbmc/linux/
H A Dopengrok1.0.log[all...]