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Searched refs:cwl (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_topology.c26 unsigned int cwl; in mv_ddr_cwl_calc() local
29 cwl = 9; in mv_ddr_cwl_calc()
31 cwl = 10; in mv_ddr_cwl_calc()
33 cwl = 11; in mv_ddr_cwl_calc()
35 cwl = 12; in mv_ddr_cwl_calc()
37 cwl = 14; in mv_ddr_cwl_calc()
39 cwl = 16; in mv_ddr_cwl_calc()
41 cwl = 0; in mv_ddr_cwl_calc()
43 return cwl; in mv_ddr_cwl_calc()
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c576 u32 reg, tmp, cwl; local
1089 cwl = 5; /* CWL = 5 */
1091 cwl = 6; /* CWL = 6 */
1093 cwl = 7; /* CWL = 7 */
1095 cwl = 8; /* CWL = 8 */
1097 cwl = 9; /* CWL = 9 */
1099 cwl = 10; /* CWL = 10 */
1101 cwl = 11; /* CWL = 11 */
1103 cwl = 12; /* CWL = 12 */
1105 cwl = 12; /* CWL = 12 */
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H A Dddr3_dfs.c998 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1184 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1496 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
H A Dddr3_hw_training.h268 u32 cwl; member
H A Dddr3_hw_training.c145 dram_info.cwl = reg; in ddr3_hw_training()
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3_spd.c122 u32 cwl; member
253 spd->cwl = 0; in ddrtimingcalculation()
255 spd->cwl = 1; in ddrtimingcalculation()
257 spd->cwl = 2; in ddrtimingcalculation()
259 spd->cwl = 3; in ddrtimingcalculation()
261 spd->cwl = 4; in ddrtimingcalculation()
263 spd->cwl = 5; in ddrtimingcalculation()
356 (spd->cwl & 7) << 3 | (spd->pasr & 7); in init_ddr3param()
370 (DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | in init_ddr3param()
/openbmc/u-boot/drivers/ddr/fsl/
H A Dctrl_regs.c89 cwl = 9; in compute_cas_write_latency()
91 cwl = 10; in compute_cas_write_latency()
93 cwl = 11; in compute_cas_write_latency()
95 cwl = 12; in compute_cas_write_latency()
97 cwl = 14; in compute_cas_write_latency()
99 cwl = 16; in compute_cas_write_latency()
124 cwl = 5; in compute_cas_write_latency()
126 cwl = 6; in compute_cas_write_latency()
128 cwl = 7; in compute_cas_write_latency()
130 cwl = 8; in compute_cas_write_latency()
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Dsmc.c262 uint8_t cwl; in ddrphy_init() local
267 cwl = 5 + mrc_params->ddr_speed; in ddrphy_init()
430 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
436 ((cwl - 2) << 0), 0x003f1f1f); in ddrphy_init()
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-lmcx-defs.h1892 uint64_t cwl:3; member
1894 uint64_t cwl:3;