Searched refs:ctl1 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_smbus-test.c | 215 uint8_t ctl1; in start_transfer() local
217 ctl1 = CTL1_START | CTL1_INTEN | CTL1_STASTRE; in start_transfer()
218 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in start_transfer()
228 uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer() local
230 ctl1 &= ~(CTL1_START | CTL1_ACK); in stop_transfer()
231 ctl1 |= CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE; in stop_transfer()
232 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in stop_transfer()
233 ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer()
234 g_assert_false(ctl1 & CTL1_STOP); in stop_transfer()
308 uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in send_nack() local
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| /openbmc/qemu/hw/i2c/ |
| H A D | npcm7xx_smbus.c | 204 if (s->ctl1 & NPCM7XX_SMBCTL1_INTEN) { in npcm7xx_smbus_update_irq()
205 level = !!((s->ctl1 & NPCM7XX_SMBCTL1_NMINTE && in npcm7xx_smbus_update_irq()
210 (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE && in npcm7xx_smbus_update_irq()
212 (s->ctl1 & NPCM7XX_SMBCTL1_EOBINTE && in npcm7xx_smbus_update_irq()
401 if (s->ctl1 & NPCM7XX_SMBCTL1_STASTRE) { in npcm7xx_smbus_send_address()
555 s->ctl1 = KEEP_OLD_BIT(s->ctl1, value, in npcm7xx_smbus_write_ctl1()
575 s->ctl1 = 0; in npcm7xx_smbus_write_ctl2()
677 value = s->ctl1; in npcm7xx_smbus_read()
999 s->ctl1 = NPCM7XX_SMB_CTL1_INIT_VAL; in npcm7xx_smbus_enter_reset()
1055 VMSTATE_UINT8(ctl1, NPCM7xxSMBusState),
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| /openbmc/qemu/include/hw/i2c/ |
| H A D | npcm7xx_smbus.h | 84 uint8_t ctl1; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx25/ |
| H A D | imx-regs.h | 55 u32 ctl1; /* control 1 */ member
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx31/ |
| H A D | imx-regs.h | 523 u32 ctl1; member
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