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Searched refs:csrw (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/riscv/kernel/
H A Dkexec_relocate.S43 csrw CSR_SIE, zero
44 csrw CSR_SIP, zero
57 csrw CSR_STVEC, s8
78 csrw CSR_SATP, zero
139 csrw CSR_SEPC, zero
140 csrw CSR_SCAUSE, zero
168 csrw CSR_SIE, zero
169 csrw CSR_SIP, zero
203 csrw CSR_SEPC, zero
213 csrw CSR_STVEC, a2
[all …]
H A Dhead.S86 csrw CSR_TVEC, a2
106 csrw CSR_SATP, a0
111 csrw CSR_TVEC, a0
125 csrw CSR_SATP, a2
134 csrw CSR_IE, zero
135 csrw CSR_IP, zero
152 csrw CSR_TVEC, a3
180 csrw CSR_TVEC, a0
199 csrw CSR_IE, zero
200 csrw CSR_IP, zero
[all …]
H A Dhibernate-asm.S26 csrw CSR_SATP, s0
63 csrw satp, s1
H A Dentry.S77 csrw CSR_SCRATCH, x0
135 csrw CSR_SCRATCH, tp
158 csrw CSR_STATUS, a0
159 csrw CSR_EPC, a2
/openbmc/qemu/tests/tcg/riscv64/
H A Dissue1060.S7 csrw mtvec, t0
10 csrw time, x0
12 csrw time, x0
14 csrw cycle, x0
29 csrw mepc, t0
/openbmc/linux/arch/riscv/include/asm/
H A Dassembler.h24 csrw CSR_EPC, t0
26 csrw CSR_STATUS, t0
28 csrw CSR_TVAL, t0
30 csrw CSR_CAUSE, t0
/openbmc/u-boot/arch/riscv/cpu/
H A Dstart.S43 csrw MODE_PREFIX(tvec), t0
46 csrw MODE_PREFIX(ie), zero
171 csrw MODE_PREFIX(tvec), t0
H A Dmtrap.S69 csrw MODE_PREFIX(epc), a0
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_switch.S67 csrw CSR_SEPC, t5
166 csrw CSR_STVEC, t1
224 csrw CSR_SEPC, a1
277 csrw CSR_SSTATUS, t2
320 csrw CSR_SSTATUS, t2
363 csrw CSR_SSTATUS, t2
406 csrw CSR_SSTATUS, t2
/openbmc/linux/drivers/mtd/nand/raw/
H A Drockchip-nand-controller.c84 #define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs)) argument
/openbmc/qemu/target/riscv/
H A Dhelper.h126 DEF_HELPER_3(csrw, void, env, int, tl)