Searched refs:csr_val (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/drivers/crypto/intel/qat/qat_common/ |
H A D | adf_gen4_pfvf.c | 89 u32 csr_val; in adf_gen4_pfvf_send() local 92 csr_val = adf_pfvf_csr_msg_of(accel_dev, msg, &csr_gen4_fmt); in adf_gen4_pfvf_send() 93 if (unlikely(!csr_val)) in adf_gen4_pfvf_send() 98 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val | ADF_PFVF_INT); in adf_gen4_pfvf_send() 101 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & ADF_PFVF_INT), in adf_gen4_pfvf_send() 117 u32 csr_val; in adf_gen4_pfvf_recv() local 120 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen4_pfvf_recv() 121 if (!(csr_val & ADF_PFVF_INT)) { in adf_gen4_pfvf_recv() 123 "Spurious PFVF interrupt, msg 0x%.8x. Ignored\n", csr_val); in adf_gen4_pfvf_recv() 130 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val & ~ADF_PFVF_INT); in adf_gen4_pfvf_recv() [all …]
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H A D | adf_gen2_pfvf.c | 122 return (csr_val >> offset) & 0xFFFF; in gen2_csr_msg_from_position() 186 u32 csr_val; in adf_gen2_pfvf_send() local 214 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_send() 225 ret = read_poll_timeout(ADF_CSR_RD, csr_val, !(csr_val & int_bit), in adf_gen2_pfvf_send() 231 csr_val &= ~int_bit; in adf_gen2_pfvf_send() 253 ADF_CSR_WR(pmisc_addr, pfvf_offset, csr_val); in adf_gen2_pfvf_send() 279 u32 csr_val; in adf_gen2_pfvf_recv() local 285 csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset); in adf_gen2_pfvf_recv() 286 if (!(csr_val & int_bit)) { in adf_gen2_pfvf_recv() 316 csr_val &= ~int_bit; in adf_gen2_pfvf_recv() [all …]
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H A D | qat_hal.c | 306 unsigned int csr_val; in qat_hal_reset() local 309 csr_val |= reset_mask; in qat_hal_reset() 342 return csr_val; in qat_hal_rd_indr_csr() 447 unsigned int csr_val; in qat_hal_init_esram() local 454 if ((csr_val & ESRAM_AUTO_TINIT) && (csr_val & ESRAM_AUTO_TINIT_DONE)) in qat_hal_init_esram() 481 unsigned int csr_val; in qat_hal_clr_reset() local 485 csr_val &= ~reset_mask; in qat_hal_clr_reset() 491 csr_val &= reset_mask; in qat_hal_clr_reset() 492 } while (csr_val); in qat_hal_clr_reset() 495 csr_val |= reset_mask; in qat_hal_clr_reset() [all …]
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/openbmc/u-boot/drivers/mtd/nand/raw/ |
H A D | zynq_nand.c | 1019 u32 csr_val; in zynq_nand_device_ready() local 1021 csr_val = readl(&zynq_nand_smc_base->csr); in zynq_nand_device_ready() 1023 if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) { in zynq_nand_device_ready()
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