Searched refs:csr_reg (Results 1 – 6 of 6) sorted by relevance
380 void __iomem *csr_reg; in xgene_pmdclk_init() local397 csr_reg = of_iomap(np, 0); in xgene_pmdclk_init()398 if (!csr_reg) { in xgene_pmdclk_init()417 if (csr_reg) in xgene_pmdclk_init()418 iounmap(csr_reg); in xgene_pmdclk_init()452 if (pclk->param.csr_reg) { in xgene_clk_enable()492 if (pclk->param.csr_reg) { in xgene_clk_disable()518 if (pclk->param.csr_reg) { in xgene_clk_is_enabled()679 parameters.csr_reg = NULL; in xgene_devclk_init()733 if (parameters.csr_reg) in xgene_devclk_init()[all …]
143 u32 csr_reg; in orinoco_plx_hw_init() local166 csr_reg = ioread32(card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()167 if (!(csr_reg & PLX_INTCSR_INTEN)) { in orinoco_plx_hw_init()168 csr_reg |= PLX_INTCSR_INTEN; in orinoco_plx_hw_init()169 iowrite32(csr_reg, card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()170 csr_reg = ioread32(card->bridge_io + PLX_INTCSR); in orinoco_plx_hw_init()171 if (!(csr_reg & PLX_INTCSR_INTEN)) { in orinoco_plx_hw_init()
40 u32 *csr_reg = ug_io_base + EXI_CSR; in ug_io_transaction() local47 out_be32(csr_reg, csr); in ug_io_transaction()59 out_be32(csr_reg, 0); in ug_io_transaction()
48 u32 __iomem *csr_reg = ug_io_base + EXI_CSR; in ug_io_transaction() local55 out_be32(csr_reg, csr); in ug_io_transaction()67 out_be32(csr_reg, 0); in ug_io_transaction()
49 csr_reg: csr { label
584 unsigned long csr_reg, csr, csr_error_bits; in schizo_pcierr_intr_other() local588 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; in schizo_pcierr_intr_other()589 csr = upa_readq(csr_reg); in schizo_pcierr_intr_other()599 upa_writeq(csr, csr_reg); in schizo_pcierr_intr_other()