Searched refs:csr_read32 (Results 1 – 9 of 9) sorted by relevance
17 saved_crmd = csr_read32(LOONGARCH_CSR_CRMD); in save_processor_state()18 saved_prmd = csr_read32(LOONGARCH_CSR_PRMD); in save_processor_state()19 saved_euen = csr_read32(LOONGARCH_CSR_EUEN); in save_processor_state()20 saved_ecfg = csr_read32(LOONGARCH_CSR_ECFG); in save_processor_state()
35 saved_regs.pwctl0 = csr_read32(LOONGARCH_CSR_PWCTL0); in loongarch_common_suspend()36 saved_regs.pwctl1 = csr_read32(LOONGARCH_CSR_PWCTL1); in loongarch_common_suspend()37 saved_regs.ecfg = csr_read32(LOONGARCH_CSR_ECFG); in loongarch_common_suspend()38 saved_regs.euen = csr_read32(LOONGARCH_CSR_EUEN); in loongarch_common_suspend()
63 return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_FPEN) ? in is_fp_enabled()72 return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_LSXEN) ? in is_lsx_enabled()81 return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_LASXEN) ? in is_lasx_enabled()183 euen = csr_read32(LOONGARCH_CSR_EUEN); in save_fpu_regs()
164 #define csr_read32(reg) __csrrd_w(reg) macro 1165 return csr_read32(LOONGARCH_CSR_CPUID);1182 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;1192 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE;1210 #define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID)1218 #define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG)1220 #define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT)1222 #define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX)1224 #define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN)1226 #define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUI[all...]
24 return (csr_read32(LOONGARCH_CSR_EUEN) & CSR_EUEN_LBTEN) ? in is_lbt_enabled()
160 p->thread.csr_crmd = csr_read32(LOONGARCH_CSR_CRMD); in copy_thread()161 p->thread.csr_prmd = csr_read32(LOONGARCH_CSR_PRMD); in copy_thread()162 p->thread.csr_ecfg = csr_read32(LOONGARCH_CSR_ECFG); in copy_thread()
494 if ((csr_read32(LOONGARCH_CSR_FWPS) & (0x1 << i))) { in watchpoint_handler() 514 if ((csr_read32(LOONGARCH_CSR_MWPS) & (0x1 << i))) { in arch_hw_breakpoint_init()
180 config = csr_read32(LOONGARCH_CSR_ASID); in cpu_probe_common()
772 int llbit = (csr_read32(LOONGARCH_CSR_LLBCTL) & 0x1); in do_watch()1037 pr_err("csr_merrctl == %08x\n", csr_read32(LOONGARCH_CSR_MERRCTL)); in cache_parity_error()