Searched refs:cscr (Results 1 – 6 of 6) sorted by relevance
48 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()59 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk() local62 if (cscr & CSCR_MCU_SEL) in imx_get_mpllclk()73 ulong cscr = readl(&pll->cscr); in imx_get_armclk() local77 if (!(cscr & CSCR_ARM_SRC_MPLL)) in imx_get_armclk()80 div = ((cscr >> 12) & 0x3) + 1; in imx_get_armclk()88 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk() local92 div = ((cscr >> 8) & 0x3) + 1; in imx_get_ahbclk()100 ulong cscr = readl(&pll->cscr); in imx_get_spllclk() local103 if (cscr & CSCR_SP_SEL) in imx_get_spllclk()
22 u32 cscr; in mx27_suspend_enter() local31 cscr = imx_readl(ccm_base); in mx27_suspend_enter()32 cscr &= 0xFFFFFFFC; in mx27_suspend_enter()33 imx_writel(cscr, ccm_base); in mx27_suspend_enter()
148 struct mx31_weim_cscr *cscr = &weim->cscr[cs]; in mxc_setup_weimcs() local150 writel(weimcs->upper, &cscr->upper); in mxc_setup_weimcs()151 writel(weimcs->lower, &cscr->lower); in mxc_setup_weimcs()152 writel(weimcs->additional, &cscr->additional); in mxc_setup_weimcs()
80 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
115 u32 cscr; /* Clock Source Control Register */ member
516 struct mx31_weim_cscr cscr[6]; member