Home
last modified time | relevance | path

Searched refs:crm (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/qemu/target/arm/
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
51 .cp = 15, .opc1 = 0, .crm = 15,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
57 .cp = 15, .opc1 = 1, .crm = 15,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
[all …]
H A Dhelper.c634 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
639 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
651 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
659 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
673 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
682 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
684 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
686 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
688 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
691 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm
6864 K(op0,op1,crn,crm,op2) define_arm_vh_e2h_redirects_aliases() argument
9677 uint8_t crm = 0b1000 | extract32(i, 1, 3); register_cp_regs_for_features() local
9707 uint8_t crm = 0b1000 | extract32(i, 1, 3); register_cp_regs_for_features() local
10015 add_cpreg_to_hashtable(ARMCPU * cpu,const ARMCPRegInfo * r,void * opaque,CPState state,CPSecureState secstate,int crm,int opc1,int opc2,const char * name) add_cpreg_to_hashtable() argument
10236 int crm, opc1, opc2; define_one_arm_cp_reg_with_opaque() local
[all...]
H A Ddebug_helper.c949 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
953 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
956 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
961 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
972 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
982 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
986 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
991 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
1000 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1010 .cp = 14, .opc1 = 0, .crn = 0, .crm
[all...]
H A Dsyndrome.h163 int crn, int crm, int rt, in syn_aa64_sysregtrap() argument
168 | (crm << 1) | isread; in syn_aa64_sysregtrap()
172 int crn, int crm, int rt, int isread, in syn_cp14_rt_trap() argument
178 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rt_trap()
182 int crn, int crm, int rt, int isread, in syn_cp15_rt_trap() argument
188 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rt_trap()
191 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp14_rrt_trap() argument
198 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rrt_trap()
201 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp15_rrt_trap() argument
208 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rrt_trap()
H A Dcpregs.h171 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
173 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
175 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ argument
181 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
861 uint8_t crm; member
1078 uint8_t crn, uint8_t crm) in arm_cpreg_encoding_in_idspace() argument
1081 crn == 0 && crm < 8; in arm_cpreg_encoding_in_idspace()
1092 ri->crn, ri->crm); in arm_cpreg_in_idspace()
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
[all …]
H A Dcpu64.c481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Da32.decode50 &mcr cp opc1 crn crm opc2 rt
51 &mcrr cp opc1 crm rt rt2
546 @mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr
547 @mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr
H A Dt32.decode48 &mcr !extern cp opc1 crn crm opc2 rt
49 &mcrr !extern cp opc1 crm rt rt2
707 @mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
708 @mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c563 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_read()
566 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_read()
575 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_write()
577 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_write()
592 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_read()
609 trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icv_bpr_read()
618 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_write()
620 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, in icv_bpr_write()
743 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_hppir_read()
760 trace_gicv3_icv_hppir_read(ri->crm in icv_hppir_read()
[all...]
H A Darm_gicv3_kvm.c51 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ argument
55 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
/openbmc/qemu/target/arm/hvf/
H A Dtrace-events1 …t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x …
2 … op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x …
6 …uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d …
7 …uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d…
/openbmc/linux/arch/arm64/tools/
H A Dgen-sysreg.awk157 crm = $6
164 define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
165 define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
170 define("SYS_" reg "_CRm", crm)
197 crm = null
/openbmc/linux/arch/arm64/include/asm/
H A Desr.h212 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
217 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
328 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument
332 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
349 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ argument
351 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
H A Dsysreg.h39 #define sys_reg(op0, op1, crn, crm, op2) \ argument
41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
420 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/openbmc/linux/tools/arch/arm/include/uapi/asm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
175 #define __ARM_CP15_REG64(op1,crm) \ argument
176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
/openbmc/qemu/linux-headers/asm-arm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
175 #define __ARM_CP15_REG64(op1,crm) \ argument
176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
/openbmc/qemu/linux-headers/asm-arm64/
H A Dkvm.h249 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
254 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
513 #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ argument
517 (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \
/openbmc/linux/tools/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
/openbmc/linux/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dget-reg-list.c185 unsigned op0, op1, crn, crm, op2; in print_reg() local
238 crm = (id & KVM_REG_ARM64_SYSREG_CRM_MASK) >> KVM_REG_ARM64_SYSREG_CRM_SHIFT; in print_reg()
240 TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2), in print_reg()
242 printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2); in print_reg()
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c326 #define ID_UNALLOCATED(crm, op2) { \ argument
327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
/openbmc/linux/arch/m68k/include/asm/
H A Dbvme6000hw.h39 pad_y[3], crm, member
/openbmc/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h36 #define sys_reg(op0, op1, crn, crm, op2) \ argument
38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
472 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h17 #define MRC14(op1, crn, crm, op2) \ argument
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\

12