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Searched refs:crm (Results 1 – 25 of 43) sorted by relevance

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/openbmc/qemu/target/arm/
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
51 .cp = 15, .opc1 = 0, .crm = 15,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
57 .cp = 15, .opc1 = 1, .crm = 15,
63 .cp = 15, .opc1 = 2, .crm = 15,
[all …]
H A Dhelper.c6155 .cp = 15, .opc1 = 6, .crm = 2,
9137 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9149 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9168 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9180 .cp = 15, .opc1 = opc1, .crn = 6, .crm = crm, .opc2 = opc2, in register_cp_regs_for_features()
9584 r2->crm = crm; in add_cpreg_to_hashtable()
9677 if (((r->crm == CP_ANY) && crm != 0) || in add_cpreg_to_hashtable()
9723 int crm, opc1, opc2; in define_one_arm_cp_reg_with_opaque() local
9724 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; in define_one_arm_cp_reg_with_opaque()
9725 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; in define_one_arm_cp_reg_with_opaque()
[all …]
H A Ddebug_helper.c942 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
960 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
970 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
998 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
1026 .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
1067 { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1070 { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1079 int i = ri->crm; in dbgwvr_write()
1104 int i = ri->crm; in dbgwcr_write()
1116 int i = ri->crm; in dbgbvr_write()
[all …]
H A Dsyndrome.h160 int crn, int crm, int rt, in syn_aa64_sysregtrap() argument
165 | (crm << 1) | isread; in syn_aa64_sysregtrap()
169 int crn, int crm, int rt, int isread, in syn_cp14_rt_trap() argument
175 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rt_trap()
179 int crn, int crm, int rt, int isread, in syn_cp15_rt_trap() argument
185 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rt_trap()
188 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp14_rrt_trap() argument
195 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rrt_trap()
198 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp15_rrt_trap() argument
205 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rrt_trap()
H A Dcpregs.h163 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
165 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
167 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ argument
173 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
848 uint8_t crm; member
1057 uint8_t crn, uint8_t crm) in arm_cpreg_encoding_in_idspace() argument
1060 crn == 0 && crm < 8; in arm_cpreg_encoding_in_idspace()
1071 ri->crn, ri->crm); in arm_cpreg_in_idspace()
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c590 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, in icv_bpr_write()
709 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_hppir_read()
790 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, in icv_iar_read()
1471 bool is_eoir0 = ri->crm == 8; in icc_eoir_write()
2312 .cp = 15, .opc1 = 0, .crm = 12,
2324 .cp = 15, .opc1 = 1, .crm = 12,
2336 .cp = 15, .opc1 = 2, .crm = 12,
2570 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_read()
2579 if (ri->crm >= 14) { in ich_lr_read()
2598 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_write()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c487 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
498 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
501 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
504 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
508 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
512 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
520 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
523 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Dcpu32.c198 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
340 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
392 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
398 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
405 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
407 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
472 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
476 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
765 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
767 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
[all …]
H A Da32.decode50 &mcr cp opc1 crn crm opc2 rt
51 &mcrr cp opc1 crm rt rt2
546 @mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr
547 @mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr
H A Dt32.decode48 &mcr !extern cp opc1 crn crm opc2 rt
49 &mcrr !extern cp opc1 crm rt rt2
708 @mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
709 @mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4
/openbmc/qemu/target/arm/hvf/
H A Dtrace-events1 …t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64": 0x%08x …
2 … op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx64": 0x%08x …
6 …uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%08x (op0=%d …
7 …uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%08x (op0=%d…
/openbmc/linux/arch/arm64/include/asm/
H A Desr.h212 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
217 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
328 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument
332 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
349 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ argument
351 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
H A Dsysreg.h39 #define sys_reg(op0, op1, crn, crm, op2) \ argument
41 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
420 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/openbmc/linux/arch/arm64/tools/
H A Dgen-sysreg.awk157 crm = $6
164 define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
165 define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
170 define("SYS_" reg "_CRm", crm)
197 crm = null
/openbmc/linux/tools/arch/arm/include/uapi/asm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
175 #define __ARM_CP15_REG64(op1,crm) \ argument
176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
/openbmc/qemu/linux-headers/asm-arm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
170 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
175 #define __ARM_CP15_REG64(op1,crm) \ argument
176 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
/openbmc/qemu/linux-headers/asm-arm64/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
/openbmc/linux/tools/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
/openbmc/linux/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
251 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dget-reg-list.c185 unsigned op0, op1, crn, crm, op2; in print_reg() local
238 crm = (id & KVM_REG_ARM64_SYSREG_CRM_MASK) >> KVM_REG_ARM64_SYSREG_CRM_SHIFT; in print_reg()
240 TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2), in print_reg()
242 printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2); in print_reg()
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c326 #define ID_UNALLOCATED(crm, op2) { \ argument
327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
/openbmc/qemu/hw/arm/
H A Dpxa2xx.c359 { .name = "CPPMNC", .cp = 14, .crn = 0, .crm = 1, .opc1 = 0, .opc2 = 0,
362 { .name = "CPCCNT", .cp = 14, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
365 { .name = "CPINTEN", .cp = 14, .crn = 4, .crm = 1, .opc1 = 0, .opc2 = 0,
367 { .name = "CPFLAG", .cp = 14, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0,
369 { .name = "CPEVTSEL", .cp = 14, .crn = 8, .crm = 1, .opc1 = 0, .opc2 = 0,
372 { .name = "CPPMN0", .cp = 14, .crn = 0, .crm = 2, .opc1 = 0, .opc2 = 0,
374 { .name = "CPPMN1", .cp = 14, .crn = 1, .crm = 2, .opc1 = 0, .opc2 = 0,
376 { .name = "CPPMN2", .cp = 14, .crn = 2, .crm = 2, .opc1 = 0, .opc2 = 0,
378 { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
381 { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dbvme6000hw.h39 pad_y[3], crm, member
/openbmc/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h36 #define sys_reg(op0, op1, crn, crm, op2) \ argument
38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
472 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) argument
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h17 #define MRC14(op1, crn, crm, op2) \ argument
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\

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