| /openbmc/qemu/accel/tcg/ |
| H A D | ldst_common.c.inc | 357 return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
377 return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
382 return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
397 return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra);
408 cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
414 cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
420 cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
426 cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
432 cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
438 cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra);
[all …]
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | mte_helper.c | 294 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
314 cpu_mmu_index(env, false), ra); in check_tag_aligned()
347 int mmu_idx = cpu_mmu_index(env, false); in do_stg()
374 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
384 int mmu_idx = cpu_mmu_index(env, false); in do_st2g()
432 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
448 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
508 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
558 int mmu_idx = cpu_mmu_index(env, false); in HELPER()
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| H A D | tlb_helper.c | 261 int mmu_idx = cpu_mmu_index(env, true); in helper_exception_pc_alignment()
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| /openbmc/qemu/target/ppc/ |
| H A D | mem_helper.c | 86 int mmu_idx = cpu_mmu_index(env, false); in helper_lmw()
108 int mmu_idx = cpu_mmu_index(env, false); in helper_stmw()
138 mmu_idx = cpu_mmu_index(env, false); in do_lsw()
227 mmu_idx = cpu_mmu_index(env, false); in helper_stsw()
279 int mmu_idx = epid ? PPC_TLB_EPID_STORE : cpu_mmu_index(env, false); in dcbz_common()
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| /openbmc/qemu/target/hppa/ |
| H A D | op_helper.c | 62 int mmu_idx = cpu_mmu_index(env, 0); in atomic_store_mask32()
89 int mmu_idx = cpu_mmu_index(env, 0); in atomic_store_mask64()
238 probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); in do_stby_e()
299 probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); in do_stdby_e()
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| H A D | cpu.h | 284 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/semihosting/ |
| H A D | uaccess.c | 29 int mmu_idx = cpu_mmu_index(env, false); in uaccess_strlen_user()
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| /openbmc/qemu/target/s390x/tcg/ |
| H A D | mem_helper.c | 361 const int mmu_idx = cpu_mmu_index(env, false); in do_helper_nc()
395 const int mmu_idx = cpu_mmu_index(env, false); in do_helper_xc()
436 const int mmu_idx = cpu_mmu_index(env, false); in do_helper_oc()
470 const int mmu_idx = cpu_mmu_index(env, false); in do_helper_mvc()
511 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
532 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
553 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
575 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
609 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
896 const int mmu_idx = cpu_mmu_index(env, false); in HELPER()
[all …]
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| /openbmc/qemu/target/hexagon/ |
| H A D | cpu.h | 152 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/target/mips/tcg/sysemu/ |
| H A D | special_helper.c | 71 switch (cpu_mmu_index(env, false)) { in debug_post_eret()
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| H A D | tlb_helper.c | 641 cpu_mmu_index(env, false)) != in walk_directory()
669 cpu_mmu_index(env, false)) != in walk_directory()
828 cpu_mmu_index(env, false)) != in page_table_walk_refill()
841 cpu_mmu_index(env, false)) != in page_table_walk_refill()
982 cpu_mmu_index(env, false)); in cpu_mips_translate_address()
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| /openbmc/qemu/target/avr/ |
| H A D | cpu.h | 188 #define cpu_mmu_index avr_cpu_mmu_index macro
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| /openbmc/qemu/target/cris/ |
| H A D | cpu.h | 263 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/target/rx/ |
| H A D | cpu.h | 164 static inline int cpu_mmu_index(CPURXState *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/target/tricore/ |
| H A D | cpu.h | 253 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) in cpu_mmu_index() function
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| H A D | helper.c | 51 int mmu_idx = cpu_mmu_index(&cpu->env, false); in tricore_cpu_get_phys_page_debug()
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| /openbmc/qemu/target/mips/sysemu/ |
| H A D | physaddr.c | 239 cpu_mmu_index(env, false)) != 0) { in mips_cpu_get_phys_page_debug()
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| /openbmc/qemu/target/nios2/ |
| H A D | cpu.h | 273 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/target/riscv/ |
| H A D | op_helper.c | 160 int mmu_idx = cpu_mmu_index(env, false); in helper_cbo_zero()
208 int mmu_idx = cpu_mmu_index(env, false); in check_zicbom_access()
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| /openbmc/qemu/target/sparc/ |
| H A D | cpu.h | 711 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) in cpu_mmu_index() function
786 flags = cpu_mmu_index(env, false); in cpu_get_tb_cpu_state()
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| /openbmc/qemu/target/microblaze/ |
| H A D | cpu.h | 437 static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) in cpu_mmu_index() function
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| H A D | mmu.c | 308 0, cpu_mmu_index(env, false)); in mmu_write()
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| H A D | helper.c | 234 int mmu_idx = cpu_mmu_index(env, false); in mb_cpu_get_phys_page_attrs_debug()
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| /openbmc/qemu/target/openrisc/ |
| H A D | cpu.h | 367 static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) in cpu_mmu_index() function
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| /openbmc/qemu/target/alpha/ |
| H A D | cpu.h | 394 static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) in cpu_mmu_index() function
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