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Searched refs:cpu1_csr (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dpsci.c46 writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); in psci_board_init()
54 while (!(readl(&flow->cpu1_csr) & CSR_PWR_OFF_STS) || in psci_board_init()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra20/
H A Dflow.h16 u32 cpu1_csr; member
/openbmc/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dflow.h16 u32 cpu1_csr; member
/openbmc/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dflow.h16 u32 cpu1_csr; member
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dflow.h17 u32 cpu1_csr; /* offset 0x18 */ member
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dflow.h17 u32 cpu1_csr; /* offset 0x18 */ member