Home
last modified time | relevance | path

Searched refs:cpu0intr (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/misc/
H A Darmsse-mhu.c60 qemu_set_irq(s->cpu0irq, s->cpu0intr != 0); in armsse_mhu_update()
71 r = s->cpu0intr; in armsse_mhu_read()
111 s->cpu0intr |= (value & INTR_MASK); in armsse_mhu_write()
114 s->cpu0intr &= ~(value & INTR_MASK); in armsse_mhu_write()
152 s->cpu0intr = 0; in armsse_mhu_reset()
161 VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
/openbmc/qemu/include/hw/misc/
H A Darmsse-mhu.h41 uint32_t cpu0intr; member