Home
last modified time | relevance | path

Searched refs:cpu (Results 1 – 25 of 1685) sorted by relevance

12345678910>>...68

/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_64r6eb.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6eb
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6eb
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6eb
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6eb
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6eb
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6eb
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6eb
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6eb
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6eb
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6eb
[all …]
H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
[all …]
H A Dtest_msa_run_64r6el.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6el
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6el
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6el
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6el
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6el
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6el
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6el
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6el
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6el
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6el
[all …]
H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
[all …]
/openbmc/qemu/accel/tcg/
H A Dtcg-accel-ops-rr.c43 CPUState *cpu; in rr_kick_vcpu_thread() local
45 CPU_FOREACH(cpu) { in rr_kick_vcpu_thread()
46 cpu_exit(cpu); in rr_kick_vcpu_thread()
73 CPUState *cpu; in rr_kick_next_cpu() local
75 cpu = qatomic_read(&rr_current_cpu); in rr_kick_next_cpu()
76 if (cpu) { in rr_kick_next_cpu()
77 cpu_exit(cpu); in rr_kick_next_cpu()
81 } while (cpu != qatomic_read(&rr_current_cpu)); in rr_kick_next_cpu()
110 CPUState *cpu; in rr_wait_io_event() local
119 CPU_FOREACH(cpu) { in rr_wait_io_event()
[all …]
H A Dcpu-exec.c70 static void align_clocks(SyncClocks *sc, CPUState *cpu) in align_clocks() argument
78 cpu_icount = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in align_clocks()
121 static void init_delay_params(SyncClocks *sc, CPUState *cpu) in init_delay_params() argument
129 = cpu->icount_extra + cpu->neg.icount_decr.u16.low; in init_delay_params()
142 static void align_clocks(SyncClocks *sc, const CPUState *cpu) in align_clocks() argument
146 static void init_delay_params(SyncClocks *sc, const CPUState *cpu) in init_delay_params() argument
194 static TranslationBlock *tb_htable_lookup(CPUState *cpu, TCGTBCPUState s) in tb_htable_lookup() argument
201 desc.env = cpu_env(cpu); in tb_htable_lookup()
226 static inline TranslationBlock *tb_lookup(CPUState *cpu, TCGTBCPUState s) in tb_lookup() argument
236 jc = cpu->tb_jmp_cache; in tb_lookup()
[all …]
H A Dtcg-accel-ops-mttcg.c40 CPUState *cpu; member
43 static void do_nothing(CPUState *cpu, run_on_cpu_data d) in do_nothing() argument
49 CPUState *cpu = container_of(notify, MttcgForceRcuNotifier, notifier)->cpu; in mttcg_force_rcu() local
55 async_run_on_cpu(cpu, do_nothing, RUN_ON_CPU_NULL); in mttcg_force_rcu()
67 CPUState *cpu = arg; in mttcg_cpu_thread_fn() local
74 force_rcu.cpu = cpu; in mttcg_cpu_thread_fn()
79 qemu_thread_get_self(cpu->thread); in mttcg_cpu_thread_fn()
81 cpu->thread_id = qemu_get_thread_id(); in mttcg_cpu_thread_fn()
82 cpu->neg.can_do_io = true; in mttcg_cpu_thread_fn()
83 current_cpu = cpu; in mttcg_cpu_thread_fn()
[all …]
H A Dcpu-exec-common.c28 bool tcg_cflags_has(CPUState *cpu, uint32_t flags) in tcg_cflags_has() argument
30 return cpu->tcg_cflags & flags; in tcg_cflags_has()
33 void tcg_cflags_set(CPUState *cpu, uint32_t flags) in tcg_cflags_set() argument
35 cpu->tcg_cflags |= flags; in tcg_cflags_set()
38 uint32_t curr_cflags(CPUState *cpu) in curr_cflags() argument
40 uint32_t cflags = cpu->tcg_cflags; in curr_cflags()
49 if (unlikely(cpu->singlestep_enabled)) { in curr_cflags()
61 void cpu_loop_exit_noexc(CPUState *cpu) in cpu_loop_exit_noexc() argument
63 cpu->exception_index = -1; in cpu_loop_exit_noexc()
64 cpu_loop_exit(cpu); in cpu_loop_exit_noexc()
[all …]
/openbmc/qemu/hw/core/
H A Dcpu-system.c34 bool cpu_has_work(CPUState *cpu) in cpu_has_work() argument
36 return cpu->cc->sysemu_ops->has_work(cpu); in cpu_has_work()
39 bool cpu_paging_enabled(const CPUState *cpu) in cpu_paging_enabled() argument
41 if (cpu->cc->sysemu_ops->get_paging_enabled) { in cpu_paging_enabled()
42 return cpu->cc->sysemu_ops->get_paging_enabled(cpu); in cpu_paging_enabled()
48 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, in cpu_get_memory_mapping() argument
51 if (cpu->cc->sysemu_ops->get_memory_mapping) { in cpu_get_memory_mapping()
52 return cpu->cc->sysemu_ops->get_memory_mapping(cpu, list, errp); in cpu_get_memory_mapping()
59 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, in cpu_get_phys_page_attrs_debug() argument
64 if (cpu->cc->sysemu_ops->get_phys_page_attrs_debug) { in cpu_get_phys_page_attrs_debug()
[all …]
H A Dcpu-common.c43 CPUState *cpu; in cpu_by_arch_id() local
45 CPU_FOREACH(cpu) { in cpu_by_arch_id()
46 if (cpu->cc->get_arch_id(cpu) == id) { in cpu_by_arch_id()
47 return cpu; in cpu_by_arch_id()
61 CPUState *cpu = CPU(object_new(typename)); in cpu_create() local
62 if (!qdev_realize(DEVICE(cpu), NULL, &err)) { in cpu_create()
64 object_unref(OBJECT(cpu)); in cpu_create()
67 return cpu; in cpu_create()
72 void cpu_reset_interrupt(CPUState *cpu, int mask) in cpu_reset_interrupt() argument
79 cpu->interrupt_request &= ~mask; in cpu_reset_interrupt()
[all …]
/openbmc/qemu/target/i386/emulate/
H A Dx86.h198 #define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg]) argument
200 #define RRX(cpu, reg) (x86_reg(cpu, reg)->rrx) argument
201 #define RAX(cpu) RRX(cpu, R_EAX) argument
202 #define RCX(cpu) RRX(cpu, R_ECX) argument
203 #define RDX(cpu) RRX(cpu, R_EDX) argument
204 #define RBX(cpu) RRX(cpu, R_EBX) argument
205 #define RSP(cpu) RRX(cpu, R_ESP) argument
206 #define RBP(cpu) RRX(cpu, R_EBP) argument
207 #define RSI(cpu) RRX(cpu, R_ESI) argument
208 #define RDI(cpu) RRX(cpu, R_EDI) argument
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
26 ARMISARegisters *isar = &cpu->isar; in aa32_max_features()
48 t = cpu->isar.mvfr1; in aa32_max_features()
51 cpu->isar.mvfr1 = t; in aa32_max_features()
53 t = cpu->isar.mvfr2; in aa32_max_features()
56 cpu->isar.mvfr2 = t; in aa32_max_features()
97 cpu->isar.dbgdidr = t; in aa32_max_features()
108 cpu->isar.dbgdevid = t; in aa32_max_features()
113 cpu->isar.dbgdevid1 = t; in aa32_max_features()
123 ARMCPU *cpu = ARM_CPU(obj); in arm926_initfn() local
[all …]
H A Dcpu64.c34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
35 ARMISARegisters *isar = &cpu->isar; in aarch64_a35_initfn()
37 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
41 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
42 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
43 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
44 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a35_initfn()
[all …]
/openbmc/qemu/system/
H A Dcpus.c77 bool cpu_is_stopped(CPUState *cpu) in cpu_is_stopped() argument
79 return cpu->stopped || !runstate_is_running(); in cpu_is_stopped()
82 bool cpu_work_list_empty(CPUState *cpu) in cpu_work_list_empty() argument
84 return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); in cpu_work_list_empty()
87 bool cpu_thread_is_idle(CPUState *cpu) in cpu_thread_is_idle() argument
89 if (cpu->stop || !cpu_work_list_empty(cpu)) { in cpu_thread_is_idle()
92 if (cpu_is_stopped(cpu)) { in cpu_thread_is_idle()
95 if (!cpu->halted || cpu_has_work(cpu)) { in cpu_thread_is_idle()
99 return cpus_accel->cpu_thread_is_idle(cpu); in cpu_thread_is_idle()
106 CPUState *cpu; in all_cpu_threads_idle() local
[all …]
/openbmc/qemu/accel/hvf/
H A Dhvf-accel-ops.c81 static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) in do_hvf_cpu_synchronize_state() argument
83 if (!cpu->vcpu_dirty) { in do_hvf_cpu_synchronize_state()
84 hvf_get_registers(cpu); in do_hvf_cpu_synchronize_state()
85 cpu->vcpu_dirty = true; in do_hvf_cpu_synchronize_state()
89 static void hvf_cpu_synchronize_state(CPUState *cpu) in hvf_cpu_synchronize_state() argument
91 if (!cpu->vcpu_dirty) { in hvf_cpu_synchronize_state()
92 run_on_cpu(cpu, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL); in hvf_cpu_synchronize_state()
96 static void do_hvf_cpu_synchronize_set_dirty(CPUState *cpu, in do_hvf_cpu_synchronize_set_dirty() argument
100 cpu->vcpu_dirty = true; in do_hvf_cpu_synchronize_set_dirty()
103 static void hvf_cpu_synchronize_post_reset(CPUState *cpu) in hvf_cpu_synchronize_post_reset() argument
[all …]
/openbmc/qemu/target/arm/
H A Dcpu64.c61 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sve_finalize() argument
78 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
79 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
92 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
93 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
95 assert(!cpu_isar_feature(aa64_sve, cpu)); in arm_cpu_sve_finalize()
99 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
111 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { in arm_cpu_sve_finalize()
115 max_vq * 128, cpu->sve_max_vq, in arm_cpu_sve_finalize()
116 cpu->sve_max_vq * 128); in arm_cpu_sve_finalize()
[all …]
/openbmc/qemu/
H A Dcpu-common.c81 void cpu_list_add(CPUState *cpu) in cpu_list_add() argument
86 if (cpu->cpu_index == UNASSIGNED_CPU_INDEX) { in cpu_list_add()
88 cpu->cpu_index = cpu_get_free_index(); in cpu_list_add()
89 assert(cpu->cpu_index != UNASSIGNED_CPU_INDEX); in cpu_list_add()
93 QTAILQ_INSERT_TAIL_RCU(&cpus_queue, cpu, node); in cpu_list_add()
97 void cpu_list_remove(CPUState *cpu) in cpu_list_remove() argument
100 if (!QTAILQ_IN_USE(cpu, node)) { in cpu_list_remove()
105 QTAILQ_REMOVE_RCU(&cpus_queue, cpu, node); in cpu_list_remove()
106 cpu->cpu_index = UNASSIGNED_CPU_INDEX; in cpu_list_remove()
112 CPUState *cpu; in qemu_get_cpu() local
[all …]
/openbmc/qemu/hw/openrisc/
H A Dcputimer.c38 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val) in cpu_openrisc_count_set() argument
45 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu) in cpu_openrisc_count_get() argument
51 void cpu_openrisc_count_update(OpenRISCCPU *cpu) in cpu_openrisc_count_update() argument
55 if (!cpu->env.is_counting) { in cpu_openrisc_count_update()
64 void cpu_openrisc_timer_update(OpenRISCCPU *cpu) in cpu_openrisc_timer_update() argument
69 if (!cpu->env.is_counting) { in cpu_openrisc_timer_update()
73 cpu_openrisc_count_update(cpu); in cpu_openrisc_timer_update()
76 if ((cpu->env.ttmr & TTMR_TP) <= (or1k_timer->ttcr & TTMR_TP)) { in cpu_openrisc_timer_update()
78 wait += cpu->env.ttmr & TTMR_TP; in cpu_openrisc_timer_update()
80 wait = (cpu->env.ttmr & TTMR_TP) - (or1k_timer->ttcr & TTMR_TP); in cpu_openrisc_timer_update()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dthunderx-88xx.dtsi24 cpu@000 {
25 device_type = "cpu";
30 cpu@001 {
31 device_type = "cpu";
36 cpu@002 {
37 device_type = "cpu";
42 cpu@003 {
43 device_type = "cpu";
48 cpu@004 {
49 device_type = "cpu";
[all …]
/openbmc/openbmc/poky/meta/recipes-support/boost/boost/
H A D0001-Don-t-set-up-arch-instruction-set-flags-we-do-that-o.patch19 @@ -1144,156 +1144,3 @@ local rule cpu-flags ( toolset variable : architecture : instruction-set + :
31 -cpu-flags gcc OPTIONS : x86 : native : -march=native ;
32 -cpu-flags gcc OPTIONS : x86 : i486 : -march=i486 ;
33 -cpu-flags gcc OPTIONS : x86 : i586 : -march=i586 ;
34 -cpu-flags gcc OPTIONS : x86 : i686 : -march=i686 ;
35 -cpu-flags gcc OPTIONS : x86 : pentium : -march=pentium ;
36 -cpu-flags gcc OPTIONS : x86 : pentium-mmx : -march=pentium-mmx ;
37 -cpu-flags gcc OPTIONS : x86 : pentiumpro : -march=pentiumpro ;
38 -cpu-flags gcc OPTIONS : x86 : pentium2 : -march=pentium2 ;
39 -cpu-flags gcc OPTIONS : x86 : pentium3 : -march=pentium3 ;
[all …]
/openbmc/qemu/target/s390x/
H A Dcpu-system.c44 S390CPU *cpu = S390_CPU(cs); in s390_cpu_has_work() local
47 if (s390_cpu_get_state(cpu) != S390_CPU_STATE_LOAD && in s390_cpu_has_work()
48 s390_cpu_get_state(cpu) != S390_CPU_STATE_OPERATING) { in s390_cpu_has_work()
56 return s390_cpu_has_int(cpu); in s390_cpu_has_work()
62 S390CPU *cpu = S390_CPU(s); in s390_cpu_load_normal() local
67 cpu->env.psw.mask = spsw & PSW_MASK_SHORT_CTRL; in s390_cpu_load_normal()
72 cpu->env.psw.mask ^= PSW_MASK_SHORTPSW; in s390_cpu_load_normal()
73 cpu->env.psw.addr = spsw & PSW_MASK_SHORT_ADDR; in s390_cpu_load_normal()
79 s390_cpu_set_state(S390_CPU_STATE_LOAD, cpu); in s390_cpu_load_normal()
81 s390_cpu_set_state(S390_CPU_STATE_OPERATING, cpu); in s390_cpu_load_normal()
[all …]
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, in riscv_cpu_write_misa_bit() argument
76 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
104 RISCVCPU *cpu = env_archcpu(env); in riscv_get_tb_cpu_state() local
109 if (cpu->cfg.ext_zve32x) { in riscv_get_tb_cpu_state()
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
180 if (cpu->cfg.debug && !icount_enabled()) { in riscv_get_tb_cpu_state()
202 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_synchronize_from_tb() local
203 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
220 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_restore_state_to_opc() local
221 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86.c49 bool x86_read_segment_descriptor(CPUState *cpu, in x86_read_segment_descriptor() argument
64 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_read_segment_descriptor()
65 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_read_segment_descriptor()
67 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_read_segment_descriptor()
68 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_read_segment_descriptor()
75 vmx_read_mem(cpu, desc, base + sel.index * 8, sizeof(*desc)); in x86_read_segment_descriptor()
79 bool x86_write_segment_descriptor(CPUState *cpu, in x86_write_segment_descriptor() argument
87 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_write_segment_descriptor()
88 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_write_segment_descriptor()
90 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_write_segment_descriptor()
[all …]
/openbmc/qemu/target/i386/whpx/
H A Dwhpx-accel-ops.c24 CPUState *cpu = arg; in whpx_cpu_thread_fn() local
30 qemu_thread_get_self(cpu->thread); in whpx_cpu_thread_fn()
31 cpu->thread_id = qemu_get_thread_id(); in whpx_cpu_thread_fn()
32 current_cpu = cpu; in whpx_cpu_thread_fn()
34 r = whpx_init_vcpu(cpu); in whpx_cpu_thread_fn()
41 cpu_thread_signal_created(cpu); in whpx_cpu_thread_fn()
42 qemu_guest_random_seed_thread_part2(cpu->random_seed); in whpx_cpu_thread_fn()
45 if (cpu_can_run(cpu)) { in whpx_cpu_thread_fn()
46 r = whpx_vcpu_exec(cpu); in whpx_cpu_thread_fn()
48 cpu_handle_guest_debug(cpu); in whpx_cpu_thread_fn()
[all …]
/openbmc/qemu/target/i386/nvmm/
H A Dnvmm-accel-ops.c22 CPUState *cpu = arg; in qemu_nvmm_cpu_thread_fn() local
30 qemu_thread_get_self(cpu->thread); in qemu_nvmm_cpu_thread_fn()
31 cpu->thread_id = qemu_get_thread_id(); in qemu_nvmm_cpu_thread_fn()
32 current_cpu = cpu; in qemu_nvmm_cpu_thread_fn()
34 r = nvmm_init_vcpu(cpu); in qemu_nvmm_cpu_thread_fn()
41 cpu_thread_signal_created(cpu); in qemu_nvmm_cpu_thread_fn()
42 qemu_guest_random_seed_thread_part2(cpu->random_seed); in qemu_nvmm_cpu_thread_fn()
45 if (cpu_can_run(cpu)) { in qemu_nvmm_cpu_thread_fn()
46 r = nvmm_vcpu_exec(cpu); in qemu_nvmm_cpu_thread_fn()
48 cpu_handle_guest_debug(cpu); in qemu_nvmm_cpu_thread_fn()
[all …]

12345678910>>...68