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Searched refs:cpll_sdiv (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init.h52 unsigned cpll_sdiv; member
H A Dclock_init_exynos5.c150 .cpll_sdiv = 0x1,
273 .cpll_sdiv = 0x2,
376 .cpll_sdiv = 0x2,
641 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); in exynos5250_system_clock_init()
870 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); in exynos5420_system_clock_init()