Searched refs:control_regs (Results 1 – 9 of 9) sorted by relevance
56 return nest_pervasive->control_regs.cplt_ctrl[i]; in pnv_chiplet_ctrl_read()67 val = nest_pervasive->control_regs.cplt_cfg0; in pnv_chiplet_ctrl_read()76 val = nest_pervasive->control_regs.cplt_cfg1; in pnv_chiplet_ctrl_read()85 val = nest_pervasive->control_regs.cplt_stat0; in pnv_chiplet_ctrl_read()88 val = nest_pervasive->control_regs.cplt_mask0; in pnv_chiplet_ctrl_read()91 val = nest_pervasive->control_regs.ctrl_protect_mode; in pnv_chiplet_ctrl_read()94 val = nest_pervasive->control_regs.ctrl_atomic_lock; in pnv_chiplet_ctrl_read()113 nest_pervasive->control_regs.cplt_ctrl[i] = val; in pnv_chiplet_ctrl_write()116 nest_pervasive->control_regs.cplt_ctrl[i] |= val; in pnv_chiplet_ctrl_write()119 nest_pervasive->control_regs.cplt_ctrl[i] &= ~val; in pnv_chiplet_ctrl_write()[all …]
163 const u16 *control_regs; member207 value = readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()212 writeb(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()215 readb(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()216 barrier_data(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()218 value = readl(priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()223 writel(value, priv->base + priv->control_regs[reg]); in cpg_mstp_clock_endisable()235 priv->base + priv->control_regs[reg], bit); in cpg_mstp_clock_endisable()257 value = readb(priv->base + priv->control_regs[clock->index / 32]); in cpg_mstp_clock_is_enabled()880 readb(priv->base + priv->control_regs[reg]) : in cpg_mssr_suspend_noirq()[all …]
213 uint32_t old_irq = s->control_regs.irqstatus; in ahci_check_irq()215 s->control_regs.irqstatus = 0; in ahci_check_irq()219 s->control_regs.irqstatus |= (1 << i); in ahci_check_irq()222 trace_ahci_check_irq(s, old_irq, s->control_regs.irqstatus); in ahci_check_irq()223 if (s->control_regs.irqstatus && in ahci_check_irq()224 (s->control_regs.ghc & HOST_CTL_IRQ_EN)) { in ahci_check_irq()406 val = s->control_regs.cap; in ahci_mem_read_32()409 val = s->control_regs.ghc; in ahci_mem_read_32()412 val = s->control_regs.irqstatus; in ahci_mem_read_32()415 val = s->control_regs.impl; in ahci_mem_read_32()[all …]
120 struct control_regs __iomem *control_regs; member135 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))254 rp = &p->control_regs->vswin; in control_set_hardware()786 info->fix.mmio_len = sizeof(struct control_regs); in control_init_info()914 if (p->control_regs) in control_cleanup()915 iounmap(p->control_regs); in control_cleanup()975 p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size); in control_of_init()984 if (!p->cmap_regs || !p->control_regs || !p->frame_buffer) in control_of_init()
40 struct control_regs { struct
29 PnvPervasiveCtrlRegs control_regs; member
43 AHCIControlRegs control_regs; member
360 } control_regs; member
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