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Searched refs:control_ddr3ch2_0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dprcm-regs.c327 .control_ddr3ch2_0 = 0x4A002E34,
419 .control_ddr3ch2_0 = 0x4A002E34,
H A Dhwinit.c81 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); in io_settings_ddr3()
/openbmc/u-boot/arch/arm/include/asm/
H A Domap_common.h416 u32 control_ddr3ch2_0; member