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Searched refs:config_reg (Results 1 – 25 of 52) sorted by relevance

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/openbmc/linux/drivers/spi/
H A Dspi-zynq-qspi.c183 u32 config_reg; in zynq_qspi_init_hw() local
189 config_reg = 0; in zynq_qspi_init_hw()
192 config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM; in zynq_qspi_init_hw()
294 u32 config_reg; in zynq_qspi_chipselect() local
300 config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE; in zynq_qspi_chipselect()
302 config_reg |= ZYNQ_QSPI_LCFG_U_PAGE; in zynq_qspi_chipselect()
310 config_reg &= ~ZYNQ_QSPI_CONFIG_PCS; in zynq_qspi_chipselect()
312 config_reg |= ZYNQ_QSPI_CONFIG_PCS; in zynq_qspi_chipselect()
336 u32 config_reg, baud_rate_val = 0; in zynq_qspi_config_op() local
358 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK; in zynq_qspi_config_op()
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H A Dspi-zynqmp-gqspi.c356 u32 config_reg, baud_rate_val = 0; in zynqmp_qspi_init_hw() local
380 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; in zynqmp_qspi_init_hw()
384 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; in zynqmp_qspi_init_hw()
388 config_reg |= GQSPI_CFG_WP_HOLD_MASK; in zynqmp_qspi_init_hw()
393 config_reg |= GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_init_hw()
395 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; in zynqmp_qspi_init_hw()
398 config_reg |= GQSPI_CFG_CLK_POL_MASK; in zynqmp_qspi_init_hw()
747 u32 config_reg, genfifoentry; in zynqmp_process_dma_irq() local
848 u32 rx_bytes, rx_rem, config_reg; in zynqmp_qspi_setuprxdma() local
908 u32 config_reg; in zynqmp_qspi_write_op() local
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/openbmc/linux/drivers/iio/common/ms_sensors/
H A Dms_sensors_i2c.c254 u8 *config_reg) in ms_sensors_read_config_reg() argument
264 ret = i2c_master_recv(client, config_reg, 1); in ms_sensors_read_config_reg()
288 u8 config_reg; in ms_sensors_write_resolution() local
295 config_reg &= 0x7E; in ms_sensors_write_resolution()
300 config_reg); in ms_sensors_write_resolution()
319 u8 config_reg; in ms_sensors_show_battery_low() local
345 u8 config_reg; in ms_sensors_show_heater() local
373 u8 val, config_reg; in ms_sensors_write_heater() local
390 config_reg &= 0xFB; in ms_sensors_write_heater()
391 config_reg |= val << 2; in ms_sensors_write_heater()
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/openbmc/qemu/hw/pci/
H A Dpci_host.c168 s->config_reg = val; in pci_host_config_write()
175 uint32_t val = s->config_reg; in pci_host_config_read()
187 if (s->config_reg & (1u << 31)) in pci_host_data_write()
188 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); in pci_host_data_write()
196 if (!(s->config_reg & (1U << 31))) { in pci_host_data_read()
199 return pci_data_read(s->bus, s->config_reg | (addr & 3), len); in pci_host_data_read()
238 VMSTATE_UINT32(config_reg, PCIHostState),
/openbmc/u-boot/board/theadorable/
H A Dfpga.c67 u32 config_reg; in fpga_write_fn() local
88 config_reg = readl(&reg->cfg); in fpga_write_fn()
98 writel(config_reg, &reg->cfg); in fpga_write_fn()
/openbmc/u-boot/drivers/gpio/
H A Dsh_pfc.c249 struct pinmux_cfg_reg *config_reg; in get_config_reg() local
255 config_reg = gpioc->cfg_regs + k; in get_config_reg()
257 r_width = config_reg->reg_width; in get_config_reg()
258 f_width = config_reg->field_width; in get_config_reg()
269 curr_width = config_reg->var_field_width[m]; in get_config_reg()
273 if (config_reg->enum_ids[pos + n] == enum_id) { in get_config_reg()
274 *crp = config_reg; in get_config_reg()
277 *cntp = &config_reg->cnt[m]; in get_config_reg()
H A Dtca642x.c122 uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg; in tca642x_set_dir() local
124 return tca642x_reg_write(chip, config_reg, reg_bit, data); in tca642x_set_dir()
147 uint8_t config_reg; in tca642x_set_inital_state() local
152 config_reg = tca642x_regs[i].configuration_reg; in tca642x_set_inital_state()
153 ret = tca642x_reg_write(chip, config_reg, 0xff, in tca642x_set_inital_state()
/openbmc/linux/drivers/net/phy/
H A Daquantia_main.c365 u32 config_reg; in aqr107_read_rate() local
380 config_reg = VEND1_GLOBAL_CFG_10M; in aqr107_read_rate()
384 config_reg = VEND1_GLOBAL_CFG_100M; in aqr107_read_rate()
388 config_reg = VEND1_GLOBAL_CFG_1G; in aqr107_read_rate()
392 config_reg = VEND1_GLOBAL_CFG_2_5G; in aqr107_read_rate()
396 config_reg = VEND1_GLOBAL_CFG_5G; in aqr107_read_rate()
400 config_reg = VEND1_GLOBAL_CFG_10G; in aqr107_read_rate()
407 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); in aqr107_read_rate()
/openbmc/linux/drivers/input/misc/
H A Dmax77693-haptic.c107 unsigned int value, config_reg; in max77693_haptic_configure() local
116 config_reg = MAX77693_HAPTIC_REG_CONFIG2; in max77693_haptic_configure()
122 config_reg = MAX77843_HAP_REG_MCONFIG; in max77693_haptic_configure()
129 config_reg, value); in max77693_haptic_configure()
/openbmc/qemu/hw/pci-host/
H A Ddino.c108 ioaddr = phb->config_reg + (addr & 3); in dino_chip_read_with_attrs()
203 ioaddr = phb->config_reg + (addr & 3); in dino_chip_write_with_attrs()
310 return pci_data_read(s->bus, s->config_reg | (addr & 3), len); in dino_config_data_read()
317 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); in dino_config_data_write()
338 s->config_reg = val & ~3U; in dino_config_addr_write()
H A Dastro.c239 val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); in elroy_config_data_read()
240 trace_elroy_pci_config_data_read(s->config_reg | (addr & 3), len, val); in elroy_config_data_read()
248 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); in elroy_config_data_write()
249 trace_elroy_pci_config_data_write(s->config_reg | (addr & 3), len, val); in elroy_config_data_write()
270 s->config_reg = val; in elroy_config_addr_write()
H A Dbonito.c502 phb->config_reg = (pciaddr) | (1u << 31); in bonito_spciconf_write()
503 pci_data_write(phb->bus, phb->config_reg, val, size); in bonito_spciconf_write()
531 phb->config_reg = (pciaddr) | (1u << 31); in bonito_spciconf_read()
538 return pci_data_read(phb->bus, phb->config_reg, size); in bonito_spciconf_read()
/openbmc/linux/drivers/hwmon/
H A Dmax6620.c99 static const u8 config_reg[] = { variable
171 ret = i2c_smbus_read_byte_data(client, config_reg[i]); in max6620_update_device()
449 reg = i2c_smbus_read_byte_data(client, config_reg[i]); in max6620_init_client()
456 err = i2c_smbus_write_byte_data(client, config_reg[i], data->fancfg[i]); in max6620_init_client()
/openbmc/u-boot/arch/arm/mach-omap2/
H A Demif-common.c643 u32 config_reg = 0; in get_sdram_config_reg() local
645 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; in get_sdram_config_reg()
646 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << in get_sdram_config_reg()
649 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; in get_sdram_config_reg()
651 config_reg |= RL << EMIF_REG_CL_SHIFT; in get_sdram_config_reg()
653 config_reg |= addressing->row_sz[cs0_device->io_width] << in get_sdram_config_reg()
656 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; in get_sdram_config_reg()
658 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << in get_sdram_config_reg()
661 config_reg |= addressing->col_sz[cs0_device->io_width] << in get_sdram_config_reg()
664 return config_reg; in get_sdram_config_reg()
/openbmc/linux/drivers/clk/qcom/
H A Dclk-hfpll.h17 u32 config_reg; member
H A Dclk-pll.c103 regmap_read(pll->clkr.regmap, pll->config_reg, &config); in clk_pll_recalc_rate()
162 regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits); in clk_pll_set_rate()
242 regmap_update_bits(regmap, pll->config_reg, mask, val); in clk_pll_configure()
H A Dclk-pll.h43 u32 config_reg; member
H A Dhfpll.c22 .config_reg = 0x14,
H A Da53-pll.c113 pll->config_reg = 0x14; in qcom_a53pll_probe()
H A Dgcc-ipq806x.c36 .config_reg = 0x30d4,
65 .config_reg = 0x3174,
94 .config_reg = 0x3154,
124 .config_reg = 0x3204,
150 .config_reg = 0x3244,
176 .config_reg = 0x3304,
201 .config_reg = 0x31d4,
246 .config_reg = 0x31b4,
265 .config_reg = 0x3194,
/openbmc/u-boot/drivers/spi/
H A Dzynqmp_gqspi.c190 u32 config_reg; in zynqmp_qspi_init_hw() local
199 config_reg = readl(&regs->confr); in zynqmp_qspi_init_hw()
200 config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK | in zynqmp_qspi_init_hw()
202 config_reg |= GQSPI_CONFIG_DMA_MODE | in zynqmp_qspi_init_hw()
205 writel(config_reg, &regs->confr); in zynqmp_qspi_init_hw()
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc.c195 const struct pinmux_cfg_reg *config_reg = in sh_pfc_get_config_reg() local
197 unsigned int r_width = config_reg->reg_width; in sh_pfc_get_config_reg()
198 unsigned int f_width = config_reg->field_width; in sh_pfc_get_config_reg()
214 curr_width = config_reg->var_field_width[m]; in sh_pfc_get_config_reg()
218 if (config_reg->enum_ids[pos + n] == enum_id) { in sh_pfc_get_config_reg()
219 *crp = config_reg; in sh_pfc_get_config_reg()
/openbmc/qemu/include/hw/pci/
H A Dpci_host.h45 uint32_t config_reg; member
/openbmc/linux/drivers/pinctrl/renesas/
H A Dcore.c252 const struct pinmux_cfg_reg *config_reg = in sh_pfc_get_config_reg() local
254 unsigned int r_width = config_reg->reg_width; in sh_pfc_get_config_reg()
255 unsigned int f_width = config_reg->field_width; in sh_pfc_get_config_reg()
271 curr_width = abs(config_reg->var_field_width[m]); in sh_pfc_get_config_reg()
272 if (config_reg->var_field_width[m] < 0) in sh_pfc_get_config_reg()
278 if (config_reg->enum_ids[pos + n] == enum_id) { in sh_pfc_get_config_reg()
279 *crp = config_reg; in sh_pfc_get_config_reg()
/openbmc/linux/drivers/i2c/busses/
H A Di2c-mlxbf.c1413 u32 config_reg; in mlxbf_i2c_init_master() local
1450 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); in mlxbf_i2c_init_master()
1451 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, in mlxbf_i2c_init_master()
1452 config_reg); in mlxbf_i2c_init_master()
1453 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); in mlxbf_i2c_init_master()
1455 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); in mlxbf_i2c_init_master()
1456 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, in mlxbf_i2c_init_master()
1457 config_reg); in mlxbf_i2c_init_master()
1458 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); in mlxbf_i2c_init_master()

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