Searched refs:code_dma_base1 (Results 1 – 4 of 4) sorted by relevance
40 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_gr_acr_bld_patch()42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
18 u32 code_dma_base1; member55 u32 code_dma_base1; member
39 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in loader_config_dump()82 nvkm_debug(subdev, "\tcodeDmaBase1 : 0x%x\n", hdr->code_dma_base1); in flcn_bl_dmem_desc_dump()
72 addr = ((u64)hdr.code_dma_base1 << 40 | hdr.code_dma_base << 8); in gm20b_pmu_acr_bld_patch()74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()104 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()