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Searched refs:cntr15clk_cnt (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_arria10.c40 u32 cntr15clk_cnt; member
97 { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
284 clk_hz /= main_cfg->cntr15clk_cnt; in cm_calc_handoff_periph_vco_clk_hz()
520 clk_hz /= main_cfg->cntr15clk_cnt; in cm_calc_safe_pll_numer()
770 writel(main_cfg->cntr15clk_cnt, in cm_full_cfg()