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Searched refs:cm_write_with_phase (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c33 static int cm_write_with_phase(u32 value, const void *reg_address, u32 mask) in cm_write_with_phase() function
267 ret = cm_write_with_phase(cfg->ddrdqsclk, in cm_basic_init()
274 ret = cm_write_with_phase(cfg->ddr2xdqsclk, in cm_basic_init()
280 ret = cm_write_with_phase(cfg->ddrdqclk, in cm_basic_init()
286 ret = cm_write_with_phase(cfg->s2fuser2clk, in cm_basic_init()