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/openbmc/u-boot/arch/arm/dts/
H A Dimx6ull.dtsi70 clocks = <&clks IMX6UL_CLK_ARM>,
71 <&clks IMX6UL_CLK_PLL2_BUS>,
72 <&clks IMX6UL_CLK_PLL2_PFD2>,
73 <&clks IMX6UL_CA7_SECONDARY_SEL>,
74 <&clks IMX6UL_CLK_STEP>,
75 <&clks IMX6UL_CLK_PLL1_SW>,
76 <&clks IMX6UL_CLK_PLL1_SYS>,
77 <&clks IMX6UL_PLL1_BYPASS>,
78 <&clks IMX6UL_CLK_PLL1>,
79 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
H A Dimx6sx.dtsi78 clocks = <&clks IMX6SX_CLK_ARM>,
79 <&clks IMX6SX_CLK_PLL2_PFD2>,
80 <&clks IMX6SX_CLK_STEP>,
81 <&clks IMX6SX_CLK_PLL1_SW>,
82 <&clks IMX6SX_CLK_PLL1_SYS>;
151 clocks = <&clks IMX6SX_CLK_OCRAM>;
168 clocks = <&clks IMX6SX_CLK_GPU>,
169 <&clks IMX6SX_CLK_GPU>,
170 <&clks IMX6SX_CLK_GPU>;
184 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
[all …]
H A Dimx6sll.dtsi67 clocks = <&clks IMX6SLL_CLK_ARM>,
68 <&clks IMX6SLL_CLK_PLL2_PFD2>,
69 <&clks IMX6SLL_CLK_STEP>,
70 <&clks IMX6SLL_CLK_PLL1_SW>,
71 <&clks IMX6SLL_CLK_PLL1_SYS>,
72 <&clks IMX6SLL_CLK_PLL1>,
73 <&clks IMX6SLL_PLL1_BYPASS>,
74 <&clks IMX6SLL_PLL1_BYPASS_SRC>;
136 clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
137 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
[all …]
H A Dimx6qdl.dtsi79 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
159 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
170 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
171 <&clks IMX6QDL_CLK_GPMI_APB>,
172 <&clks IMX6QDL_CLK_GPMI_BCH>,
173 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
174 <&clks IMX6QDL_CLK_PER1_BCH>;
188 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
189 <&clks IMX6QDL_CLK_HDMI_ISFR>;
214 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
[all …]
H A Dimx6ul.dtsi74 clocks = <&clks IMX6UL_CLK_ARM>,
75 <&clks IMX6UL_CLK_PLL2_BUS>,
76 <&clks IMX6UL_CLK_PLL2_PFD2>,
77 <&clks IMX6UL_CA7_SECONDARY_SEL>,
78 <&clks IMX6UL_CLK_STEP>,
79 <&clks IMX6UL_CLK_PLL1_SW>,
80 <&clks IMX6UL_CLK_PLL1_SYS>,
81 <&clks IMX6UL_PLL1_BYPASS>,
82 <&clks IMX6UL_CLK_PLL1>,
83 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
H A Dimx6qp.dtsi12 clocks = <&clks IMX6QDL_CLK_OCRAM>;
18 clocks = <&clks IMX6QDL_CLK_OCRAM>;
26 clocks = <&clks IMX6QDL_CLK_PRE0>;
35 clocks = <&clks IMX6QDL_CLK_PRE1>;
44 clocks = <&clks IMX6QDL_CLK_PRE2>;
53 clocks = <&clks IMX6QDL_CLK_PRE3>;
61 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
62 <&clks IMX6QDL_CLK_PRG0_AXI>;
70 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
71 <&clks IMX6QDL_CLK_PRG1_AXI>;
[all …]
H A Dimx6q.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
76 clocks = <&clks IMX6QDL_CLK_ARM>,
77 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
78 <&clks IMX6QDL_CLK_STEP>,
79 <&clks IMX6QDL_CLK_PLL1_SW>,
80 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
H A Dimx7ulp.dtsi159 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
193 clocks = <&clks IMX7ULP_CLK_SNVS>;
201 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
209 clocks = <&clks IMX7ULP_CLK_LPIT1>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
219 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
231 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
[all …]
H A Dimx6sl.dtsi68 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
69 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
70 <&clks IMX6SL_CLK_PLL1_SYS>;
115 clocks = <&clks IMX6SL_CLK_OCRAM>;
155 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
156 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
157 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
158 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
159 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
174 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
H A Dimx7s.dtsi102 clocks = <&clks IMX7D_CLK_ARM>;
122 clocks = <&clks IMX7D_USB_PHY1_CLK>;
129 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
196 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
228 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
241 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
278 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
305 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
319 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
437 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
[all …]
H A Dimx6dl.dtsi37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
67 clocks = <&clks IMX6QDL_CLK_ARM>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
69 <&clks IMX6QDL_CLK_STEP>,
70 <&clks IMX6QDL_CLK_PLL1_SW>,
71 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
H A Dimx53.dtsi70 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
71 <&clks IMX5_CLK_DUMMY>,
72 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
82 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
83 <&clks IMX5_CLK_DUMMY>,
84 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
105 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
106 <&clks IMX5_CLK_UART2_PER_GATE>;
113 clks: ccm@53fd4000{ label
196 clocks = <&clks IMX5_CLK_I2C3_GATE>;
[all …]
H A Dimx7s-warp.dts73 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
78 &clks {
79 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
203 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
220 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
221 <&clks IMX7D_SAI1_ROOT_CLK>;
222 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
230 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
231 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
238 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
[all …]
H A Dimx7d.dtsi77 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
94 clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
106 clocks = <&clks IMX7D_USB_CTRL_CLK>;
121 clocks = <&clks IMX7D_USB_PHY2_CLK>;
131 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
132 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
133 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
134 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
135 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
H A Dimx6q-logicpd.dts140 &clks {
141 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
142 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
143 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
144 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
145 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
146 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
147 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
148 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
H A Dimx6qdl-sabreauto.dtsi243 &clks {
244 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
245 <&clks IMX6QDL_PLL4_BYPASS>,
246 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
247 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
248 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
249 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
250 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
251 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
252 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_sandbox_test.c12 struct clk clks[SANDBOX_CLK_TEST_ID_COUNT]; member
29 &sbct->clks[i]); in sandbox_clk_test_get()
51 return clk_get_rate(&sbct->clks[id]); in sandbox_clk_test_get_rate()
61 return clk_set_rate(&sbct->clks[id], rate); in sandbox_clk_test_set_rate()
71 return clk_enable(&sbct->clks[id]); in sandbox_clk_test_enable()
88 return clk_disable(&sbct->clks[id]); in sandbox_clk_test_disable()
104 ret = clk_free(&sbct->clks[i]); in sandbox_clk_test_free()
125 if (!clk_valid(&sbct->clks[i])) in sandbox_clk_test_valid()
H A Dclk-uclass.c116 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); in clk_get_bulk()
117 if (!bulk->clks) in clk_get_bulk()
121 ret = clk_get_by_index(dev, i, &bulk->clks[i]); in clk_get_bulk()
131 err = clk_release_all(bulk->clks, bulk->count); in clk_get_bulk()
384 ret = clk_enable(&bulk->clks[i]); in clk_enable_bulk()
409 ret = clk_disable(&bulk->clks[i]); in clk_disable_bulk()
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c25 struct clk_bulk clks; member
45 if (plat->clks.count == 0) in socfpga_a10_clk_get_upstream()
48 if (plat->clks.count == 1) { in socfpga_a10_clk_get_upstream()
49 *upclk = &plat->clks.clks[0]; in socfpga_a10_clk_get_upstream()
77 *upclk = &plat->clks.clks[reg]; in socfpga_a10_clk_get_upstream()
191 struct clk_bulk *bulk = &plat->clks; in socfpga_a10_handoff_workaround()
215 bulk->clks = devm_kcalloc(dev, bulk->count, in socfpga_a10_handoff_workaround()
217 if (!bulk->clks) in socfpga_a10_handoff_workaround()
220 ret = clk_request(dev, &bulk->clks[0]); in socfpga_a10_handoff_workaround()
222 free(bulk->clks); in socfpga_a10_handoff_workaround()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Ddwc3-of-simple.c20 struct clk_bulk clks; member
49 ret = clk_get_bulk(dev, &simple->clks); in dwc3_of_simple_clk_init()
56 ret = clk_enable_bulk(&simple->clks); in dwc3_of_simple_clk_init()
58 clk_release_bulk(&simple->clks); in dwc3_of_simple_clk_init()
88 clk_release_bulk(&simple->clks); in dwc3_of_simple_remove()
/openbmc/u-boot/drivers/clk/mvebu/
H A Darmada-37xx-periph.c54 const struct clk_periph *clks; member
246 const struct clk_periph *clk = &priv->clks[id]; in get_parent_rate()
303 const struct clk_periph *clk = &priv->clks[id]; in periph_clk_get_rate()
335 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in periph_clk_enable()
389 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in armada_37xx_periph_clk_set_rate()
437 const struct clk_periph *periph_clk = &priv->clks[clk->id]; in armada_37xx_periph_clk_set_parent()
470 const struct clk_periph *clks; in armada_37xx_periph_clk_dump() local
476 clks = priv->clks; in armada_37xx_periph_clk_dump()
479 printf(" %s at %lu Hz\n", clks[i].name, in armada_37xx_periph_clk_dump()
522 const struct clk_periph *clks; in armada_37xx_periph_clk_probe() local
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dutil.c87 unsigned long long clks, clks_rem; in picos_to_mclk() local
95 clks = picos * (unsigned long long)data_rate; in picos_to_mclk()
100 clks_rem = do_div(clks, UL_5POW12); in picos_to_mclk()
101 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; in picos_to_mclk()
102 clks >>= 13; in picos_to_mclk()
106 clks++; in picos_to_mclk()
109 if (clks > ULL_8FS) in picos_to_mclk()
110 clks = ULL_8FS; in picos_to_mclk()
111 return (unsigned int) clks; in picos_to_mclk()
/openbmc/u-boot/drivers/mmc/
H A Daspeed_sdhci_ic.c29 struct clk_bulk clks; member
36 return clk_get_bulk(dev, &priv->clks); in aspeed_sdhci_irq_ofdata_to_platdata()
50 ret = clk_enable_bulk(&priv->clks); in aspeed_sdhci_irq_probe()
/openbmc/u-boot/drivers/power/domain/
H A Dmeson-gx-pwrc-vpu.c34 struct clk_bulk clks; member
87 ret = clk_enable_bulk(&priv->clks); in meson_gx_pwrc_vpu_on()
125 clk_disable_bulk(&priv->clks); in meson_gx_pwrc_vpu_off()
184 ret = clk_get_bulk(dev, &priv->clks); in meson_gx_pwrc_vpu_probe()
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3288-board.c275 } clks[] = { in do_clock() local
296 for (i = 0; i < ARRAY_SIZE(clks); i++) { in do_clock()
300 clk.id = clks[i].id; in do_clock()
306 printf("%s: %lu\n", clks[i].name, rate); in do_clock()

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