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Searched refs:clk_sel (Results 1 – 25 of 32) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/arm1136/mx35/
H A Dgeneric.c252 u32 ret_val = 0, pdf, pre_pdf, clk_sel; in mxc_get_peri_clock() local
263 clk_sel = mpdr3 & (1 << 14); in mxc_get_peri_clock()
265 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) : in mxc_get_peri_clock()
271 clk_sel = mpdr2 & (1 << 6); in mxc_get_peri_clock()
279 clk_sel = mpdr2 & (1 << 6); in mxc_get_peri_clock()
285 clk_sel = mpdr2 & (1 << 7); in mxc_get_peri_clock()
292 clk_sel = (pre_pdf & 0x80); in mxc_get_peri_clock()
300 clk_sel = mpdr3 & 0x40; in mxc_get_peri_clock()
306 clk_sel = mpdr3 & 0x40; in mxc_get_peri_clock()
312 clk_sel = mpdr3 & 0x40; in mxc_get_peri_clock()
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c322 static u32 get_standard_pll_sel_clk(u32 clk_sel) in get_standard_pll_sel_clk() argument
326 switch (clk_sel & 0x3) { in get_standard_pll_sel_clk()
349 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
352 clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg); in get_uart_clk()
353 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
368 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
375 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
385 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
797 s32 shift = 0, clk_sel, div = 1; in config_ddr_clk() local
808 clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr); in config_ddr_clk()
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dboard_common.c174 u32 clk_sel = readl(0x1e6e2300); in aspeed_mmc_init() local
221 clk_sel &= ~(0x7 << 12); in aspeed_mmc_init()
222 clk_sel |= (i << 12) | BIT(11); in aspeed_mmc_init()
223 writel(clk_sel, 0x1e6e2300); in aspeed_mmc_init()
/openbmc/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-ldb.c101 struct clk *clk_sel[4]; /* parent of display clock */ member
187 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
201 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_enable()
209 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
210 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
215 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
264 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_atomic_mode_set()
660 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); in imx_ldb_probe()
661 if (IS_ERR(imx_ldb->clk_sel[i])) { in imx_ldb_probe()
662 ret = PTR_ERR(imx_ldb->clk_sel[i]); in imx_ldb_probe()
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-gpio-defs.h53 uint64_t clk_sel:2; member
67 uint64_t clk_sel:2;
97 uint64_t clk_sel:2; member
111 uint64_t clk_sel:2;
360 uint64_t clk_sel:2; member
374 uint64_t clk_sel:2;
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c491 u32 div = (clk_sel >> 28) & 0x7; in ast2600_get_sdio_clk_rate()
494 if (clk_sel & BIT(8)) in ast2600_get_sdio_clk_rate()
511 u32 div = (clk_sel >> 12) & 0x7; in ast2600_get_emmc_clk_rate()
1280 writel(clk_sel, &scu->clk_sel1); in ast2600_configure_rsa_ecc_clk()
1327 clk_sel &= ~SCU_CLK_SD_MASK; in ast2600_enable_extsdclk()
1329 writel(clk_sel, &scu->clk_sel4); in ast2600_enable_extsdclk()
1388 clk_sel &= ~SCU_CLK_EMMC_MASK; in ast2600_enable_extemmcclk()
1390 writel(clk_sel, &scu->clk_sel1); in ast2600_enable_extemmcclk()
1402 clk_sel &= ~SCU_CLK_EMMC_MASK; in ast2600_enable_extemmcclk()
1403 clk_sel |= SCU_CLK_EMMC_DIV(i); in ast2600_enable_extemmcclk()
[all …]
H A Dclk_ast2400.c202 u32 clk_sel = readl(&scu->clk_sel1); in ast2400_get_sdio_clk_rate() local
203 u32 div = (clk_sel >> 12) & 0x7; in ast2400_get_sdio_clk_rate()
456 u32 clk_sel = readl(&scu->clk_sel1); in ast2400_enable_extsdclk() local
462 clk_sel &= ~SCU_CLK_SD_MASK; in ast2400_enable_extsdclk()
463 clk_sel |= SCU_CLK_SD_DIV(1); in ast2400_enable_extsdclk()
464 writel(clk_sel, &scu->clk_sel1); in ast2400_enable_extsdclk()
H A Dclk_ast2500.c160 u32 clk_sel = readl(&scu->clk_sel1); in ast2500_get_sdio_clk_rate() local
161 u32 div = (clk_sel >> 12) & 0x7; in ast2500_get_sdio_clk_rate()
528 u32 clk_sel = readl(&scu->clk_sel1); in ast2500_enable_extsdclk() local
534 clk_sel &= ~SCU_CLK_SD_MASK; in ast2500_enable_extsdclk()
535 clk_sel |= SCU_CLK_SD_DIV(1); in ast2500_enable_extsdclk()
536 writel(clk_sel, &scu->clk_sel1); in ast2500_enable_extsdclk()
/openbmc/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.c282 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_start_phy_polling()
306 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_read_phy_core() local
315 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_read_phy_core()
320 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
326 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
339 atl1c_start_phy_polling(hw, clk_sel); in atl1c_read_phy_core()
355 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_write_phy_core() local
363 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_write_phy_core()
369 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_write_phy_core()
375 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_write_phy_core()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c83 uint32_t clk_sel = 0; in dccg2_get_dccg_ref_freq() local
85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
/openbmc/linux/drivers/leds/rgb/
H A Dleds-qcom-lpg.c144 unsigned int clk_sel; member
272 unsigned int clk_sel, clk_len, best_clk = 0; in lpg_calc_freq() local
336 for (clk_sel = 1; clk_sel < clk_len; clk_sel++) { in lpg_calc_freq()
337 u64 numerator = period * clk_rate_arr[clk_sel]; in lpg_calc_freq()
354 clk_rate_arr[clk_sel]); in lpg_calc_freq()
360 best_clk = clk_sel; in lpg_calc_freq()
367 chan->clk_sel = best_clk; in lpg_calc_freq()
383 clk_rate = lpg_clk_rates_hi_res[chan->clk_sel]; in lpg_calc_duty()
386 clk_rate = lpg_clk_rates[chan->clk_sel]; in lpg_calc_duty()
403 val = chan->clk_sel; in lpg_apply_freq()
/openbmc/linux/drivers/iio/adc/
H A Dvf610_adc.c103 enum clk_sel { enum
141 enum clk_sel clk_sel; member
238 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; in vf610_adc_cfg_init()
258 switch (adc_feature->clk_sel) { in vf610_adc_cfg_post_set()
379 switch (adc_feature->clk_sel) { in vf610_adc_sample_set()
H A Dstm32-adc-core.c76 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); member
791 ret = priv->cfg->clk_sel(pdev, priv); in stm32_adc_probe()
864 .clk_sel = stm32f4_adc_clk_sel,
872 .clk_sel = stm32h7_adc_clk_sel,
881 .clk_sel = stm32h7_adc_clk_sel,
890 .clk_sel = stm32h7_adc_clk_sel,
/openbmc/linux/drivers/gpio/
H A Dgpio-npcm-sgpio.c53 unsigned int *clk_sel; member
297 iowrite8(clk_cfg->clk_sel[i] | tmp, in npcm_sgpio_setup_clk()
588 .clk_sel = npcm750_CLK_SEL,
594 .clk_sel = npcm845_CLK_SEL,
/openbmc/linux/drivers/net/ethernet/atheros/alx/
H A Dhw.c64 u32 val, clk_sel; in alx_read_phy_core() local
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
81 clk_sel << ALX_MDIO_CLK_SEL_SHIFT; in alx_read_phy_core()
84 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_read_phy_core()
101 u32 val, clk_sel; in alx_write_phy_core() local
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
114 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
119 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
/openbmc/linux/drivers/tty/serial/
H A Dsamsung_tty.c1423 unsigned int clk_sel) in s3c24xx_serial_setsource() argument
1436 ucon |= clk_sel << info->clksel_shift; in s3c24xx_serial_setsource()
1453 if (ourport->cfg->clk_sel && in s3c24xx_serial_getclk()
1454 !(ourport->cfg->clk_sel & (1 << cnt))) in s3c24xx_serial_getclk()
1542 unsigned int baud, quot, clk_sel = 0; in s3c24xx_serial_set_termios() local
1569 s3c24xx_serial_setsource(port, clk_sel); in s3c24xx_serial_set_termios()
1870 unsigned int clk_sel; in s3c24xx_serial_enable_baudclk() local
1875 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; in s3c24xx_serial_enable_baudclk()
1877 if (!(clk_sel & (1 << clk_num))) in s3c24xx_serial_enable_baudclk()
2398 unsigned int clk_sel; in s3c24xx_serial_get_options() local
[all …]
/openbmc/linux/sound/soc/sti/
H A Duniperif_player.c957 if (player->clk_sel) { in uni_player_resume()
958 ret = regmap_field_write(player->clk_sel, 1); in uni_player_resume()
1031 player->clk_sel = regmap_field_alloc(regmap, regfield[0]); in uni_player_parse_dt_audio_glue()
1083 if (player->clk_sel) { in uni_player_init()
1084 ret = regmap_field_write(player->clk_sel, 1); in uni_player_init()
/openbmc/linux/drivers/video/fbdev/
H A Dgrvga.c42 int clk_sel; member
112 par->clk_sel = i; in grvga_check_var()
180 __raw_writel((par->clk_sel << 6) | (func << 4) | 1, in grvga_set_par()
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c983 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0; in get_usdhc_clk() local
1001 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL; in get_usdhc_clk()
1007 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL; in get_usdhc_clk()
1013 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL; in get_usdhc_clk()
1019 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL; in get_usdhc_clk()
1026 if (clk_sel) in get_usdhc_clk()
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx93.c18 enum clk_sel { enum
54 enum clk_sel sel;
/openbmc/linux/drivers/clk/ralink/
H A Dclk-mt7621.c261 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; in mt7621_cpu_recalc_rate() local
266 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg); in mt7621_cpu_recalc_rate()
272 switch (clk_sel) { in mt7621_cpu_recalc_rate()
/openbmc/linux/drivers/spi/
H A Dspi-sunplus-sp7021.c287 u32 clk_rate, clk_sel, div; in sp7021_spi_setup_clk() local
292 clk_sel = (div / 2) - 1; in sp7021_spi_setup_clk()
294 pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel); in sp7021_spi_setup_clk()
H A Dspi-geni-qcom.c361 u32 clk_sel, m_clk_cfg, idx, div; in geni_spi_set_clock_and_bw() local
383 clk_sel = idx & CLK_SEL_MSK; in geni_spi_set_clock_and_bw()
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
/openbmc/linux/include/linux/
H A Dserial_s3c.h284 unsigned int clk_sel; member
/openbmc/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c67 u32 clk_sel; member
702 data->clk_sel = readl(data->reg + CLK_SEL); in armada_3700_periph_clock_suspend()
718 writel(data->clk_sel, data->reg + CLK_SEL); in armada_3700_periph_clock_resume()

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