Searched refs:clk_readl (Results 1 – 14 of 14) sorted by relevance
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_ssc_program()364 v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program()399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()406 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_program()456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program()741 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_autoidle_read()775 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_allow_idle()800 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_deny_idle()884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_core_dpll_save_context()[all …]
60 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()95 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & in _omap2_module_wait_ready()220 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_enable()226 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()250 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_disable()276 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_is_enabled()
50 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()55 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()63 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()94 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()108 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()241 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()267 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()273 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in omap2_apll_enable()297 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable()315 v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); in omap2_apll_set_autoidle()
49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
36 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_allow_idle()51 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_deny_idle()
213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent()249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap2_get_dpll_rate()
151 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable()162 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable()181 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable()191 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable()209 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled()743 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); in ti_clk_is_in_standby()
121 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _allow_autoidle()135 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _deny_autoidle()
99 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in ti_clk_divider_recalc_rate()256 val = ti_clk_ll_ops->clk_readl(÷r->reg); in ti_clk_divider_set_rate()277 val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift; in clk_divider_save_context()294 val = ti_clk_ll_ops->clk_readl(÷r->reg); in clk_divider_restore_context()
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()76 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
108 ops->clk_readl = clk_memmap_readl; in ti_clk_setup_ll_ops()347 ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ in ti_clk_latch()
74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
140 omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg); in omap2_reprogram_dpllcore()
245 u32 (*clk_readl)(const struct clk_omap_reg *reg); member