Searched refs:clk_mux_pcieaxi_p (Results 1 – 1 of 1) sorted by relevance
387 clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", }; variable457 { HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,458 ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,