Searched refs:clk_mux_ldi0_p (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/hisilicon/ |
| H A D | clk-hi3660.c | 245 clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv", variable
290 { HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
291 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
293 { HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
294 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
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| H A D | clk-hi3670.c | 762 clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media", variable
789 { HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
790 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
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