Searched refs:clk_mux_edc0_p (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/hisilicon/ |
| H A D | clk-hi3660.c | 240 clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv", variable
302 { HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
303 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
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| H A D | clk-hi3670.c | 756 clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media", variable
786 { HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
787 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
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