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Searched refs:clk_ctrl (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.c101 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) in zynq_clk_get_cpu_pll() argument
103 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_cpu_pll()
116 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) in zynq_clk_get_peripheral_pll() argument
118 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_peripheral_pll()
133 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
135 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_pll_rate()
137 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; in zynq_clk_get_pll_rate()
138 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; in zynq_clk_get_pll_rate()
142 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()
146 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
[all …]
H A Dclk_zynqmp.c246 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) in zynqmp_clk_get_cpu_pll() argument
248 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_cpu_pll()
262 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) in zynqmp_clk_get_ddr_pll() argument
264 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_ddr_pll()
276 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) in zynqmp_clk_get_peripheral_pll() argument
278 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_peripheral_pll()
292 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl) in zynqmp_clk_get_wdt_pll() argument
294 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_wdt_pll()
308 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, in zynqmp_clk_get_pll_src() argument
315 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >> in zynqmp_clk_get_pll_src()
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c385 u32 clk_ctrl; in cpu_mux_select() local
394 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | in cpu_mux_select()
401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
403 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
411 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | in cpu_mux_select()
415 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
417 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch3_speed.c32 struct ccsr_clk_ctrl __iomem *clk_ctrl = in get_sys_info() local
117 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) in get_sys_info()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/armada100/
H A Dtimer.c18 u32 clk_ctrl; /* Timer clk control reg */ member
111 writel(0x0, &armd1timers->clk_ctrl); in timer_init()
/openbmc/u-boot/drivers/spi/
H A Dti_qspi.c84 u32 clk_ctrl; member
132 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()
133 &priv->base->clk_ctrl); in ti_spi_set_speed()
135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()