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Searched refs:clk_ctrl (Results 1 – 25 of 41) sorted by relevance

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/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.c101 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) in zynq_clk_get_cpu_pll() argument
103 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_cpu_pll()
116 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) in zynq_clk_get_peripheral_pll() argument
118 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_peripheral_pll()
133 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local
135 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_pll_rate()
137 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; in zynq_clk_get_pll_rate()
138 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; in zynq_clk_get_pll_rate()
142 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()
146 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()
[all …]
H A Dclk_zynqmp.c246 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) in zynqmp_clk_get_cpu_pll() argument
248 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_cpu_pll()
262 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) in zynqmp_clk_get_ddr_pll() argument
264 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_ddr_pll()
276 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) in zynqmp_clk_get_peripheral_pll() argument
278 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_peripheral_pll()
292 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl) in zynqmp_clk_get_wdt_pll() argument
294 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_wdt_pll()
308 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, in zynqmp_clk_get_pll_src() argument
315 src_sel = (clk_ctrl & PLLCTRL_PRE_SRC_MASK) >> in zynqmp_clk_get_pll_src()
[all …]
/openbmc/linux/arch/mips/ath79/
H A Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
307 clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_clocks_init()
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
312 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_clocks_init()
314 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
322 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_clocks_init()
324 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
332 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_clocks_init()
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_0_sm8550.h84 .clk_ctrl = DPU_CLK_CTRL_VIG0,
92 .clk_ctrl = DPU_CLK_CTRL_VIG1,
100 .clk_ctrl = DPU_CLK_CTRL_VIG2,
108 .clk_ctrl = DPU_CLK_CTRL_VIG3,
116 .clk_ctrl = DPU_CLK_CTRL_DMA0,
124 .clk_ctrl = DPU_CLK_CTRL_DMA1,
132 .clk_ctrl = DPU_CLK_CTRL_DMA2,
140 .clk_ctrl = DPU_CLK_CTRL_DMA3,
148 .clk_ctrl = DPU_CLK_CTRL_DMA4,
156 .clk_ctrl
[all...]
H A Ddpu_3_0_msm8998.h76 .clk_ctrl = DPU_CLK_CTRL_VIG0,
84 .clk_ctrl = DPU_CLK_CTRL_VIG1,
92 .clk_ctrl = DPU_CLK_CTRL_VIG2,
100 .clk_ctrl = DPU_CLK_CTRL_VIG3,
108 .clk_ctrl = DPU_CLK_CTRL_DMA0,
116 .clk_ctrl = DPU_CLK_CTRL_DMA1,
124 .clk_ctrl = DPU_CLK_CTRL_DMA2,
132 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_4_0_sdm845.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_7_0_sm8350.h82 .clk_ctrl = DPU_CLK_CTRL_VIG0,
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
98 .clk_ctrl = DPU_CLK_CTRL_VIG2,
106 .clk_ctrl = DPU_CLK_CTRL_VIG3,
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
130 .clk_ctrl = DPU_CLK_CTRL_DMA2,
138 .clk_ctrl = DPU_CLK_CTRL_DMA3,
317 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_6_0_sm8250.h82 .clk_ctrl = DPU_CLK_CTRL_VIG0,
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
98 .clk_ctrl = DPU_CLK_CTRL_VIG2,
106 .clk_ctrl = DPU_CLK_CTRL_VIG3,
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
130 .clk_ctrl = DPU_CLK_CTRL_DMA2,
138 .clk_ctrl = DPU_CLK_CTRL_DMA3,
352 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_1_sm8450.h83 .clk_ctrl = DPU_CLK_CTRL_VIG0,
91 .clk_ctrl = DPU_CLK_CTRL_VIG1,
99 .clk_ctrl = DPU_CLK_CTRL_VIG2,
107 .clk_ctrl = DPU_CLK_CTRL_VIG3,
115 .clk_ctrl = DPU_CLK_CTRL_DMA0,
123 .clk_ctrl = DPU_CLK_CTRL_DMA1,
131 .clk_ctrl = DPU_CLK_CTRL_DMA2,
139 .clk_ctrl = DPU_CLK_CTRL_DMA3,
337 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_5_0_sm8150.h83 .clk_ctrl = DPU_CLK_CTRL_VIG0,
91 .clk_ctrl = DPU_CLK_CTRL_VIG1,
99 .clk_ctrl = DPU_CLK_CTRL_VIG2,
107 .clk_ctrl = DPU_CLK_CTRL_VIG3,
115 .clk_ctrl = DPU_CLK_CTRL_DMA0,
123 .clk_ctrl = DPU_CLK_CTRL_DMA1,
131 .clk_ctrl = DPU_CLK_CTRL_DMA2,
139 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_6_2_sc7180.h59 .clk_ctrl = DPU_CLK_CTRL_VIG0,
67 .clk_ctrl = DPU_CLK_CTRL_DMA0,
75 .clk_ctrl = DPU_CLK_CTRL_DMA1,
83 .clk_ctrl = DPU_CLK_CTRL_DMA2,
166 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_5_1_sc8180x.h82 .clk_ctrl = DPU_CLK_CTRL_VIG0,
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
98 .clk_ctrl = DPU_CLK_CTRL_VIG2,
106 .clk_ctrl = DPU_CLK_CTRL_VIG3,
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
130 .clk_ctrl = DPU_CLK_CTRL_DMA2,
138 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_8_0_sc8280xp.h82 .clk_ctrl = DPU_CLK_CTRL_VIG0,
90 .clk_ctrl = DPU_CLK_CTRL_VIG1,
98 .clk_ctrl = DPU_CLK_CTRL_VIG2,
106 .clk_ctrl = DPU_CLK_CTRL_VIG3,
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
122 .clk_ctrl = DPU_CLK_CTRL_DMA1,
130 .clk_ctrl = DPU_CLK_CTRL_DMA2,
138 .clk_ctrl = DPU_CLK_CTRL_DMA3,
H A Ddpu_7_2_sc7280.h64 .clk_ctrl = DPU_CLK_CTRL_VIG0,
72 .clk_ctrl = DPU_CLK_CTRL_DMA0,
80 .clk_ctrl = DPU_CLK_CTRL_DMA1,
88 .clk_ctrl = DPU_CLK_CTRL_DMA2,
179 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_6_4_sm6350.h66 .clk_ctrl = DPU_CLK_CTRL_VIG0,
74 .clk_ctrl = DPU_CLK_CTRL_DMA0,
82 .clk_ctrl = DPU_CLK_CTRL_DMA1,
90 .clk_ctrl = DPU_CLK_CTRL_DMA2,
H A Ddpu_5_4_sm6125.h75 .clk_ctrl = DPU_CLK_CTRL_VIG0,
83 .clk_ctrl = DPU_CLK_CTRL_DMA0,
91 .clk_ctrl = DPU_CLK_CTRL_DMA1,
H A Ddpu_6_5_qcm2290.h45 .clk_ctrl = DPU_CLK_CTRL_VIG0,
53 .clk_ctrl = DPU_CLK_CTRL_DMA0,
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_vbif.h19 u32 clk_ctrl; member
25 u32 clk_ctrl; member
40 u32 clk_ctrl; member
H A Ddpu_hw_top.c67 enum dpu_clk_ctrl_type clk_ctrl, bool enable) in dpu_hw_setup_clk_force_ctrl() argument
79 if (clk_ctrl <= DPU_CLK_CTRL_NONE || clk_ctrl >= DPU_CLK_CTRL_MAX) in dpu_hw_setup_clk_force_ctrl()
82 reg_off = mdp->caps->clk_ctrls[clk_ctrl].reg_off; in dpu_hw_setup_clk_force_ctrl()
83 bit_off = mdp->caps->clk_ctrls[clk_ctrl].bit_off; in dpu_hw_setup_clk_force_ctrl()
H A Ddpu_vbif.c203 forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); in dpu_vbif_set_ot_limit()
216 mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); in dpu_vbif_set_ot_limit()
254 forced_on = mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, true); in dpu_vbif_set_qos_remap()
265 mdp->ops.setup_clk_force_ctrl(mdp, params->clk_ctrl, false); in dpu_vbif_set_qos_remap()
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c385 u32 clk_ctrl; in cpu_mux_select() local
394 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | in cpu_mux_select()
401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
403 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
411 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | in cpu_mux_select()
415 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
417 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
/openbmc/linux/include/linux/platform_data/
H A Dnet-cw1200.h21 int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata, member
38 int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata, member
/openbmc/linux/drivers/net/wireless/st/cw1200/
H A Dcw1200_sdio.c191 if (pdata->clk_ctrl) in cw1200_sdio_off()
192 pdata->clk_ctrl(pdata, false); in cw1200_sdio_off()
220 if (pdata->clk_ctrl) { in cw1200_sdio_on()
221 if (pdata->clk_ctrl(pdata, true)) { in cw1200_sdio_on()
H A Dcw1200_spi.c288 if (pdata->clk_ctrl) in cw1200_spi_off()
289 pdata->clk_ctrl(pdata, false); in cw1200_spi_off()
317 if (pdata->clk_ctrl) { in cw1200_spi_on()
318 if (pdata->clk_ctrl(pdata, true)) { in cw1200_spi_on()
/openbmc/linux/sound/soc/codecs/
H A Dadau1372.c790 unsigned int clk_ctrl = ADAU1372_CLK_CTRL_MCLK_EN; in adau1372_set_power() local
807 clk_ctrl |= ADAU1372_CLK_CTRL_CLKSRC; in adau1372_set_power()
811 ADAU1372_CLK_CTRL_MCLK_EN | ADAU1372_CLK_CTRL_CLKSRC, clk_ctrl); in adau1372_set_power()
919 unsigned int clk_ctrl; in adau1372_probe() local
956 clk_ctrl = ADAU1372_CLK_CTRL_CC_MDIV; in adau1372_probe()
959 clk_ctrl = 0; in adau1372_probe()
962 clk_ctrl = 0; in adau1372_probe()
976 regmap_update_bits(regmap, ADAU1372_REG_CLK_CTRL, ADAU1372_CLK_CTRL_CC_MDIV, clk_ctrl); in adau1372_probe()

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