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Searched refs:clidr (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/arch/arm64/include/asm/
H A Dcache.h15 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) argument
16 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) argument
17 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) argument
22 #define CLIDR_CTYPE(clidr, level) \ argument
23 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
117 u64 clidr = read_sysreg(clidr_el1); in read_cpuid_effective_cachetype() local
119 if (CLIDR_LOC(clidr) == 0 || in read_cpuid_effective_cachetype()
120 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) in read_cpuid_effective_cachetype()
/openbmc/linux/arch/arm64/kernel/
H A Dcacheinfo.c26 u64 clidr; in get_cache_type() local
30 clidr = read_sysreg(clidr_el1); in get_cache_type()
31 return CLIDR_CTYPE(clidr, level); in get_cache_type()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S27 mrc p15, 1, r0, c0, c0, 1 @ read clidr
29 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
98 mrc p15, 1, r0, c0, c0, 1 @ read clidr
100 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
105 mov r1, r0, lsr r2 @ extract cache type bits from clidr
H A Dpsci.S193 mrc p15, 1, r0, c0, c0, 1 @ read clidr
194 ands r3, r0, #0x7000000 @ extract loc from clidr
200 mov r1, r0, lsr r2 @ extract cache type bits from clidr
/openbmc/linux/arch/arm/mm/
H A Dcache-v7.S100 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
103 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
128 mrc p15, 1, r0, c0, c0, 1 @ read clidr
130 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
136 mov r1, r0, lsr r2 @ extract cache type bits from clidr
H A Dcache-v7m.S178 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
184 mov r1, r0, lsr r2 @ extract cache type bits from clidr
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c99 cpu->clidr = 0x0a200023; in aarch64_a35_initfn()
243 cpu->clidr = 0x82000023; in aarch64_a55_initfn()
340 cpu->clidr = 0x0a200023; in aarch64_a72_initfn()
368 cpu->clidr = 0x82000023; in aarch64_a76_initfn()
451 cpu->clidr = 0x0000000080000023; in aarch64_a64fx_initfn()
608 cpu->clidr = 0x82000023; in aarch64_neoverse_n1_initfn()
680 cpu->clidr = 0x82000023; in aarch64_neoverse_v1_initfn()
937 cpu->clidr = 0x0000001482000023ull; in aarch64_a710_initfn()
1035 cpu->clidr = 0x0000001482000023ull; in aarch64_neoverse_n2_initfn()
1121 u = cpu->clidr; in aarch64_max_tcg_initfn()
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H A Dcpu-v7m.c194 cpu->clidr = 0x00000000; in cortex_m33_initfn()
231 cpu->clidr = 0x00000000; /* caches not implemented */ in cortex_m55_initfn()
H A Dcpu32.c374 cpu->clidr = (1 << 27) | (2 << 24) | 3; in cortex_a8_initfn()
449 cpu->clidr = (1 << 27) | (1 << 24) | 3; in cortex_a9_initfn()
520 cpu->clidr = 0x0a200023; in cortex_a7_initfn()
567 cpu->clidr = 0x0a200023; in cortex_a15_initfn()
756 cpu->clidr = (1 << 27) | (1 << 24) | 0x3; in cortex_r52_initfn()
987 cpu->clidr = 0x0a200023; in arm_max_initfn()
/openbmc/linux/arch/arm64/kvm/
H A Dsys_regs.c1669 u64 clidr; in reset_clidr() local
1682 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc); in reset_clidr()
1690 clidr = 1 << CLIDR_LOUU_SHIFT; in reset_clidr()
1691 clidr |= 1 << CLIDR_LOUIS_SHIFT; in reset_clidr()
1692 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1); in reset_clidr()
1701 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1); in reset_clidr()
1703 clidr |= loc << CLIDR_LOC_SHIFT; in reset_clidr()
1711 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc); in reset_clidr()
1713 __vcpu_sys_reg(vcpu, r->reg) = clidr; in reset_clidr()
/openbmc/qemu/target/arm/
H A Dcpu64.c644 cpu->clidr = 0x0a200023; in aarch64_a57_initfn()
702 cpu->clidr = 0x0a200023; in aarch64_a53_initfn()
H A Dcpu.h1045 uint64_t clidr; member
3004 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; in arm_v7m_csselr_razwi()
H A Dhelper.c8844 ARMCPRegInfo clidr = { in register_cp_regs_for_features() local
8850 .resetvalue = cpu->clidr in register_cp_regs_for_features()
8852 define_one_arm_cp_reg(cpu, &clidr); in register_cp_regs_for_features()
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1333 return cpu->clidr; in nvic_readl()