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Searched refs:cl_cwl_table (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c105 struct dram_sun9i_cl_cwl_timing *cl_cwl_table; member
435 if ((para->cl_cwl_table[i].tCKmin <= tCK) && in mctl_channel_init()
436 (tCK < para->cl_cwl_table[i].tCKmax)) { in mctl_channel_init()
437 CL = para->cl_cwl_table[i].CL; in mctl_channel_init()
438 CWL = para->cl_cwl_table[i].CWL; in mctl_channel_init()
879 .cl_cwl_table = cl_cwl, in sunxi_dram_init()