Searched refs:cfgr_reg (Results 1 – 1 of 1) sorted by relevance
350 u32 cfgr_reg = SSD2828_CFGR_EOT | /* EOT Packet Enable */ in ssd2828_init() local368 read_hw_register(cfg, SSD2828_CFGR) != cfgr_reg) { in ssd2828_init()386 cfgr_reg |= SSD2828_CFGR_CSS; in ssd2828_init()398 cfgr_reg &= ~SSD2828_CFGR_HS; /* Data lanes are in LP mode */ in ssd2828_init()399 cfgr_reg |= SSD2828_CFGR_CKE; /* Clock lane is in HS mode */ in ssd2828_init()400 cfgr_reg |= SSD2828_CFGR_DCS; /* Only use DCS packets */ in ssd2828_init()401 write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); in ssd2828_init()430 cfgr_reg |= SSD2828_CFGR_HS; /* Enable HS mode for data lanes */ in ssd2828_init()431 cfgr_reg |= SSD2828_CFGR_VEN; /* Enable video pipeline */ in ssd2828_init()432 write_hw_register(cfg, SSD2828_CFGR, cfgr_reg); in ssd2828_init()