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Searched refs:cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_offset.h10330 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT … macro
H A Dnbio_4_3_0_offset.h15127 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT … macro