Searched refs:cause1 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-imx/mx7ulp/ |
| H A D | soc.c | 177 u32 cause1, cause = 0, srs = 0; in get_reset_cause() local
185 cause1 = readl(reg_ssrs); in get_reset_cause()
186 writel(cause1, reg_ssrs); in get_reset_cause()
188 reset_cause = cause1; in get_reset_cause()
190 cause = cause1 & (CMC_SRS_POR | CMC_SRS_WUP | CMC_SRS_WARM); in get_reset_cause()
200 cause = cause1 & (CMC_SRS_WDG | CMC_SRS_SW | in get_reset_cause()
218 sprintf(ret, "%s-%X", "UNKN", cause1); in get_reset_cause()
222 debug("[%X] SRS[%X] %X - ", cause1, srs, srs^cause1); in get_reset_cause()
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| /openbmc/linux/arch/xtensa/kernel/ |
| H A D | s32c1i_selftest.c | 57 int n, cause1, cause2; in check_s32c1i() local
72 cause1 = rcw_exc; in check_s32c1i()
75 if (cause1 != 0) { in check_s32c1i()
98 if (cause1 || cause2) { in check_s32c1i()
99 pr_warn("S32C1I took exception %d, %d\n", cause1, cause2); in check_s32c1i()
105 if (cause1 != cause2) in check_s32c1i()
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