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Searched refs:cache_mem (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/cxl/
H A Dcxl-host.c105 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, in cxl_hdm_find_target() argument
114 cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY); in cxl_hdm_find_target()
123 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc); in cxl_hdm_find_target()
124 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc); in cxl_hdm_find_target()
126 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc); in cxl_hdm_find_target()
127 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc); in cxl_hdm_find_target()
133 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc); in cxl_hdm_find_target()
143 uint32_t val = ldl_le_p(cache_mem + in cxl_hdm_find_target()
148 uint32_t val = ldl_le_p(cache_mem + in cxl_hdm_find_target()
165 uint32_t *cache_mem; in cxl_cfmws_find_device() local
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H A Dcxl-component-utils.c95 uint32_t *cache_mem = cregs->cache_mem_registers; in dumb_hdm_handler() local
118 stl_le_p((uint8_t *)cache_mem + offset, value); in dumb_hdm_handler()
202 memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cxl_cstate, in cxl_component_register_block_init()
208 &cregs->cache_mem); in cxl_component_register_block_init()
/openbmc/qemu/hw/mem/
H A Dcxl_type3.c421 uint32_t *cache_mem = cregs->cache_mem_registers; in hdm_decoder_commit() local
424 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc); in hdm_decoder_commit()
429 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); in hdm_decoder_commit()
436 uint32_t *cache_mem = cregs->cache_mem_registers; in hdm_decoder_uncommit() local
439 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc); in hdm_decoder_uncommit()
444 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); in hdm_decoder_uncommit()
513 uint32_t *cache_mem = cregs->cache_mem_registers; in ct3d_reg_write() local
544 uint32_t capctrl = ldl_le_p(cache_mem + R_CXL_RAS_ERR_CAP_CTRL); in ct3d_reg_write()
584 uint32_t *header_log = &cache_mem[R_CXL_RAS_ERR_HEADER0]; in ct3d_reg_write()
603 stl_le_p((uint8_t *)cache_mem + A_CXL_RAS_ERR_CAP_CTRL, capctrl); in ct3d_reg_write()
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/openbmc/qemu/include/hw/cxl/
H A Dcxl_component.h226 MemoryRegion cache_mem; member