Searched refs:c9_pmcr (Results 1 – 3 of 3) sorted by relevance
1285 *val = env->cp15.c9_pmcr; in hvf_sysreg_read() 1456 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_counter_enabled() 1474 enabled = (env->cp15.c9_pmcr & PMCRE) && in pmu_counter_enabled() 1591 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in hvf_sysreg_write() 1592 env->cp15.c9_pmcr |= (val & PMCR_WRITABLE_MASK); in hvf_sysreg_write()
1210 e = env->cp15.c9_pmcr & PMCRE; in pmu_counter_enabled() 1230 prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; in pmu_counter_enabled() 1282 qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && in pmu_update_irq() 1294 return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; in pmccntr_clockdiv_enabled() 1320 return env->cp15.c9_pmcr & PMCRLP; in pmevcntr_is_64_bit() 1341 uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ in pmccntr_op_start() 1364 if (!(env->cp15.c9_pmcr & PMCRLC)) { in pmccntr_op_finish() 1501 env->cp15.c9_pmcr &= ~PMCR_WRITABLE_MASK; in pmcr_write() 1502 env->cp15.c9_pmcr |= (value & PMCR_WRITABLE_MASK); in pmcr_write() 1509 uint64_t pmcr = env->cp15.c9_pmcr; in pmcr_read() [all...]
387 uint64_t c9_pmcr; /* performance monitor control register */386 uint64_t c9_pmcr; /* performance monitor control register */ global() member