1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <hwconfig.h>
9 #include <pci.h>
10 #include <i2c.h>
11 #include <asm/processor.h>
12 #include <asm/mmu.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_pci.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/io.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_lbc.h>
20 #include <asm/mp.h>
21 #include <miiphy.h>
22 #include <linux/libfdt.h>
23 #include <fdt_support.h>
24 #include <fsl_mdio.h>
25 #include <tsec.h>
26 #include <vsc7385.h>
27 #include <ioports.h>
28 #include <asm/fsl_serdes.h>
29 #include <netdev.h>
30
31 #ifdef CONFIG_QE
32
33 #define GPIO_GETH_SW_PORT 1
34 #define GPIO_GETH_SW_PIN 29
35 #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
36
37 #define GPIO_SLIC_PORT 1
38 #define GPIO_SLIC_PIN 30
39 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
40
41 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
42 #define GPIO_DDR_RST_PORT 1
43 #define GPIO_DDR_RST_PIN 8
44 #define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
45
46 #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
47 #endif
48
49 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
50 #define PCA_IOPORT_I2C_ADDR 0x23
51 #define PCA_IOPORT_OUTPUT_CMD 0x2
52 #define PCA_IOPORT_CFG_CMD 0x6
53 #define PCA_IOPORT_QE_PIN_ENABLE 0xf8
54 #define PCA_IOPORT_QE_TDM_ENABLE 0xf6
55 #endif
56
57 const qe_iop_conf_t qe_iop_conf_tab[] = {
58 /* GPIO */
59 {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
60 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
61 {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
62 #endif
63 {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
64 {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
65 {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
66
67 #ifdef CONFIG_TARGET_P1025RDB
68 /* QE_MUX_MDC */
69 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
70
71 /* QE_MUX_MDIO */
72 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
73
74 /* UCC_1_MII */
75 {0, 23, 2, 0, 2}, /* CLK12 */
76 {0, 24, 2, 0, 1}, /* CLK9 */
77 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
78 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
79 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
80 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
81 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
82 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
83 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
84 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
85 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
86 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
87 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
88 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
89 {0, 17, 2, 0, 2}, /* ENET1_CRS */
90 {0, 16, 2, 0, 2}, /* ENET1_COL */
91
92 /* UCC_5_RMII */
93 {1, 11, 2, 0, 1}, /* CLK13 */
94 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
95 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
96 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
97 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
98 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
99 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
100 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
101 #endif
102
103 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
104 };
105 #endif
106
107 struct cpld_data {
108 u8 cpld_rev_major;
109 u8 pcba_rev;
110 u8 wd_cfg;
111 u8 rst_bps_sw;
112 u8 load_default_n;
113 u8 rst_bps_wd;
114 u8 bypass_enable;
115 u8 bps_led;
116 u8 status_led; /* offset: 0x8 */
117 u8 fxo_led; /* offset: 0x9 */
118 u8 fxs_led; /* offset: 0xa */
119 u8 rev4[2];
120 u8 system_rst; /* offset: 0xd */
121 u8 bps_out;
122 u8 rev5[3];
123 u8 cpld_rev_minor;
124 };
125
126 #define CPLD_WD_CFG 0x03
127 #define CPLD_RST_BSW 0x00
128 #define CPLD_RST_BWD 0x00
129 #define CPLD_BYPASS_EN 0x03
130 #define CPLD_STATUS_LED 0x01
131 #define CPLD_FXO_LED 0x01
132 #define CPLD_FXS_LED 0x0F
133 #define CPLD_SYS_RST 0x00
134
board_cpld_init(void)135 void board_cpld_init(void)
136 {
137 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
138
139 out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
140 out_8(&cpld_data->status_led, CPLD_STATUS_LED);
141 out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
142 out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
143 out_8(&cpld_data->system_rst, CPLD_SYS_RST);
144 }
145
board_gpio_init(void)146 void board_gpio_init(void)
147 {
148 #ifdef CONFIG_QE
149 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
150 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
151
152 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
153 /* reset DDR3 */
154 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
155 udelay(1000);
156 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
157 udelay(1000);
158 setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
159 /* disable CE_PB8 */
160 clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
161 #endif
162 /* Enable VSC7385 switch */
163 setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
164
165 /* Enable SLIC */
166 setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
167 #else
168
169 ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
170
171 /*
172 * GPIO10 DDR Reset, open drain
173 * GPIO7 LOAD_DEFAULT_N Input
174 * GPIO11 WDI (watchdog input)
175 * GPIO12 Ethernet Switch Reset
176 * GPIO13 SLIC Reset
177 */
178
179 setbits_be32(&pgpio->gpdir, 0x02130000);
180 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
181 /* init DDR3 reset signal */
182 setbits_be32(&pgpio->gpdir, 0x00200000);
183 setbits_be32(&pgpio->gpodr, 0x00200000);
184 clrbits_be32(&pgpio->gpdat, 0x00200000);
185 udelay(1000);
186 setbits_be32(&pgpio->gpdat, 0x00200000);
187 udelay(1000);
188 clrbits_be32(&pgpio->gpdir, 0x00200000);
189 #endif
190
191 #ifdef CONFIG_VSC7385_ENET
192 /* reset VSC7385 Switch */
193 setbits_be32(&pgpio->gpdir, 0x00080000);
194 setbits_be32(&pgpio->gpdat, 0x00080000);
195 #endif
196
197 #ifdef CONFIG_SLIC
198 /* reset SLIC */
199 setbits_be32(&pgpio->gpdir, 0x00040000);
200 setbits_be32(&pgpio->gpdat, 0x00040000);
201 #endif
202 #endif
203 }
204
board_early_init_f(void)205 int board_early_init_f(void)
206 {
207 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
208
209 setbits_be32(&gur->pmuxcr,
210 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
211 clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
212
213 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
214 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
215
216 board_gpio_init();
217 board_cpld_init();
218
219 return 0;
220 }
221
checkboard(void)222 int checkboard(void)
223 {
224 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
225 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
226 u8 in, out, io_config, val;
227
228 printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
229 in_8(&cpld_data->cpld_rev_major) & 0x0F,
230 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
231 in_8(&cpld_data->pcba_rev) & 0x0F);
232
233 /* Initialize i2c early for rom_loc and flash bank information */
234 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
235
236 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
237 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
238 i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
239 printf("Error reading i2c boot information!\n");
240 return 0; /* Don't want to hang() on this error */
241 }
242
243 val = (in & io_config) | (out & (~io_config));
244
245 puts("rom_loc: ");
246 if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
247 puts("sd");
248 #ifdef __SW_BOOT_SPI
249 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
250 puts("spi");
251 #endif
252 #ifdef __SW_BOOT_NAND
253 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
254 puts("nand");
255 #endif
256 #ifdef __SW_BOOT_PCIE
257 } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
258 puts("pcie");
259 #endif
260 } else {
261 if (val & 0x2)
262 puts("nor lower bank");
263 else
264 puts("nor upper bank");
265 }
266 puts("\n");
267
268 if (val & 0x1) {
269 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
270 puts("SD/MMC : 8-bit Mode\n");
271 puts("eSPI : Disabled\n");
272 } else {
273 puts("SD/MMC : 4-bit Mode\n");
274 puts("eSPI : Enabled\n");
275 }
276
277 return 0;
278 }
279
280 #ifdef CONFIG_PCI
pci_init_board(void)281 void pci_init_board(void)
282 {
283 fsl_pcie_init_board(0);
284 }
285 #endif
286
board_early_init_r(void)287 int board_early_init_r(void)
288 {
289 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
290 int flash_esel = find_tlb_idx((void *)flashbase, 1);
291
292 /*
293 * Remap Boot flash region to caching-inhibited
294 * so that flash can be erased properly.
295 */
296
297 /* Flush d-cache and invalidate i-cache of any FLASH data */
298 flush_dcache();
299 invalidate_icache();
300
301 if (flash_esel == -1) {
302 /* very unlikely unless something is messed up */
303 puts("Error: Could not find TLB for FLASH BASE\n");
304 flash_esel = 2; /* give our best effort to continue */
305 } else {
306 /* invalidate existing TLB entry for flash */
307 disable_tlb(flash_esel);
308 }
309
310 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
311 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
312 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
313 return 0;
314 }
315
board_eth_init(bd_t * bis)316 int board_eth_init(bd_t *bis)
317 {
318 struct fsl_pq_mdio_info mdio_info;
319 struct tsec_info_struct tsec_info[4];
320 ccsr_gur_t *gur __attribute__((unused)) =
321 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
322 int num = 0;
323 #ifdef CONFIG_VSC7385_ENET
324 char *tmp;
325 unsigned int vscfw_addr;
326 #endif
327
328 #ifdef CONFIG_TSEC1
329 SET_STD_TSEC_INFO(tsec_info[num], 1);
330 num++;
331 #endif
332 #ifdef CONFIG_TSEC2
333 SET_STD_TSEC_INFO(tsec_info[num], 2);
334 if (is_serdes_configured(SGMII_TSEC2)) {
335 printf("eTSEC2 is in sgmii mode.\n");
336 tsec_info[num].flags |= TSEC_SGMII;
337 }
338 num++;
339 #endif
340 #ifdef CONFIG_TSEC3
341 SET_STD_TSEC_INFO(tsec_info[num], 3);
342 num++;
343 #endif
344
345 if (!num) {
346 printf("No TSECs initialized\n");
347 return 0;
348 }
349
350 #ifdef CONFIG_VSC7385_ENET
351 /* If a VSC7385 microcode image is present, then upload it. */
352 tmp = env_get("vscfw_addr");
353 if (tmp) {
354 vscfw_addr = simple_strtoul(tmp, NULL, 16);
355 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
356 if (vsc7385_upload_firmware((void *) vscfw_addr,
357 CONFIG_VSC7385_IMAGE_SIZE))
358 puts("Failure uploading VSC7385 microcode.\n");
359 } else
360 puts("No address specified for VSC7385 microcode.\n");
361 #endif
362
363 mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
364 mdio_info.name = DEFAULT_MII_NAME;
365
366 fsl_pq_mdio_init(bis, &mdio_info);
367
368 tsec_eth_init(bis, tsec_info, num);
369
370 #if defined(CONFIG_UEC_ETH)
371 /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
372 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
373 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
374
375 uec_standard_init(bis);
376 #endif
377
378 return pci_eth_init(bis);
379 }
380
381 #if defined(CONFIG_QE) && \
382 (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
fdt_board_fixup_qe_pins(void * blob)383 static void fdt_board_fixup_qe_pins(void *blob)
384 {
385 unsigned int oldbus;
386 u8 val8;
387 int node;
388 fsl_lbc_t *lbc = LBC_BASE_ADDR;
389
390 if (hwconfig("qe")) {
391 /* For QE and eLBC pins multiplexing,
392 * there is a PCA9555 device on P1025RDB.
393 * It control the multiplex pins' functions,
394 * and setting the PCA9555 can switch the
395 * function between QE and eLBC.
396 */
397 oldbus = i2c_get_bus_num();
398 i2c_set_bus_num(0);
399 if (hwconfig("tdm"))
400 val8 = PCA_IOPORT_QE_TDM_ENABLE;
401 else
402 val8 = PCA_IOPORT_QE_PIN_ENABLE;
403 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
404 1, &val8, 1);
405 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
406 1, &val8, 1);
407 i2c_set_bus_num(oldbus);
408 /* if run QE TDM, Set ABSWP to implement
409 * conversion of addresses in the eLBC.
410 */
411 if (hwconfig("tdm")) {
412 set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
413 set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
414 setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
415 }
416 } else {
417 node = fdt_path_offset(blob, "/qe");
418 if (node >= 0)
419 fdt_del_node(blob, node);
420 }
421
422 return;
423 }
424 #endif
425
426 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)427 int ft_board_setup(void *blob, bd_t *bd)
428 {
429 phys_addr_t base;
430 phys_size_t size;
431 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
432 const char *soc_usb_compat = "fsl-usb2-dr";
433 int usb_err, usb1_off, usb2_off;
434 #endif
435 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
436 int err;
437 #endif
438
439 ft_cpu_setup(blob, bd);
440
441 base = env_get_bootm_low();
442 size = env_get_bootm_size();
443
444 fdt_fixup_memory(blob, (u64)base, (u64)size);
445
446 FT_FSL_PCI_SETUP;
447
448 #ifdef CONFIG_QE
449 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
450 sizeof("okay"), 0);
451 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
452 fdt_board_fixup_qe_pins(blob);
453 #endif
454 #endif
455
456 #if defined(CONFIG_HAS_FSL_DR_USB)
457 fsl_fdt_fixup_dr_usb(blob, bd);
458 #endif
459
460 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
461 /* Delete eLBC node as it is muxed with USB2 controller */
462 if (hwconfig("usb2")) {
463 const char *soc_elbc_compat = "fsl,p1020-elbc";
464 int off = fdt_node_offset_by_compatible(blob, -1,
465 soc_elbc_compat);
466 if (off < 0) {
467 printf("WARNING: could not find compatible node %s\n",
468 soc_elbc_compat);
469 return off;
470 }
471 err = fdt_del_node(blob, off);
472 if (err < 0) {
473 printf("WARNING: could not remove %s\n",
474 soc_elbc_compat);
475 return err;
476 }
477 return 0;
478 }
479 #endif
480
481 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
482 /* Delete USB2 node as it is muxed with eLBC */
483 usb1_off = fdt_node_offset_by_compatible(blob, -1,
484 soc_usb_compat);
485 if (usb1_off < 0) {
486 printf("WARNING: could not find compatible node %s\n",
487 soc_usb_compat);
488 return usb1_off;
489 }
490 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
491 soc_usb_compat);
492 if (usb2_off < 0) {
493 printf("WARNING: could not find compatible node %s\n",
494 soc_usb_compat);
495 return usb2_off;
496 }
497 usb_err = fdt_del_node(blob, usb2_off);
498 if (usb_err < 0) {
499 printf("WARNING: could not remove %s\n", soc_usb_compat);
500 return usb_err;
501 }
502 #endif
503
504 return 0;
505 }
506 #endif
507