Searched refs:bits_per_lane_and_dclk_cycle (Results 1 – 5 of 5) sorted by relevance
100 if (cfg->bits_per_lane_and_dclk_cycle == 7) { in mixel_lvds_phy_power_on()191 if (mst_cfg->bits_per_lane_and_dclk_cycle != in mixel_lvds_phy_check_slave()192 slv_cfg->bits_per_lane_and_dclk_cycle) { in mixel_lvds_phy_check_slave()194 mst_cfg->bits_per_lane_and_dclk_cycle, in mixel_lvds_phy_check_slave()195 slv_cfg->bits_per_lane_and_dclk_cycle); in mixel_lvds_phy_check_slave()234 if (cfg->bits_per_lane_and_dclk_cycle != 7 && in mixel_lvds_phy_validate()235 cfg->bits_per_lane_and_dclk_cycle != 10) { in mixel_lvds_phy_validate()237 cfg->bits_per_lane_and_dclk_cycle); in mixel_lvds_phy_validate()
464 if (lvds_cfg->bits_per_lane_and_dclk_cycle != 7) { in mixel_dphy_validate_lvds_phy()466 lvds_cfg->bits_per_lane_and_dclk_cycle); in mixel_dphy_validate_lvds_phy()
26 unsigned int bits_per_lane_and_dclk_cycle; member
72 phy_cfg->bits_per_lane_and_dclk_cycle = 7; in imx8qm_ldb_set_phy_cfg()
69 phy_cfg->bits_per_lane_and_dclk_cycle = 7; in imx8qxp_ldb_set_phy_cfg()