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Searched refs:base_addr (Results 1 – 25 of 120) sorted by relevance

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/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_smbus-test.c161 static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) in choose_bank() argument
163 uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3); in choose_bank()
171 qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); in choose_bank()
174 static void check_running(QTestState *qts, uint64_t base_addr) in check_running() argument
176 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_running()
177 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_running()
180 static void check_stopped(QTestState *qts, uint64_t base_addr) in check_stopped() argument
184 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); in check_stopped()
185 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_stopped()
186 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_stopped()
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H A Dbcm2835-i2c-test.c39 static void bcm2835_i2c_init_transfer(uint32_t base_addr, bool read) in bcm2835_i2c_init_transfer() argument
44 writel(base_addr + BCM2835_I2C_C, in bcm2835_i2c_init_transfer()
53 uint32_t base_addr = bsc_base_addrs[index]; in test_i2c_read_write() local
56 writel(base_addr + BCM2835_I2C_A, 0x50); in test_i2c_read_write()
57 writel(base_addr + BCM2835_I2C_DLEN, 3); in test_i2c_read_write()
59 bcm2835_i2c_init_transfer(base_addr, 0); in test_i2c_read_write()
61 writel(base_addr + BCM2835_I2C_FIFO, TMP105_REG_T_HIGH); in test_i2c_read_write()
62 writel(base_addr + BCM2835_I2C_FIFO, 0xde); in test_i2c_read_write()
63 writel(base_addr + BCM2835_I2C_FIFO, 0xad); in test_i2c_read_write()
66 writel(base_addr + BCM2835_I2C_S, BCM2835_I2C_S_DONE | BCM2835_I2C_S_ERR | in test_i2c_read_write()
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H A Dnpcm_gmac-test.c32 uint64_t base_addr; member
43 .base_addr = 0xf0802000
47 .base_addr = 0xf0804000
51 .base_addr = 0xf0806000
55 .base_addr = 0xf0808000
182 return qtest_readl(qts, mod->base_addr + regno); in gmac_read()
260 if (mod->base_addr == 0xf0802000) { in test_init()
H A Dhexloader-test.c23 const unsigned int base_addr = 0x00010000; in hex_loader_test() local
29 uint8_t val = qtest_readb(s, base_addr + i); in hex_loader_test()
H A Daspeed_fsi-test.c55 static void test_fsi_setup(QTestState *s, uint32_t base_addr) in test_fsi_setup() argument
59 aspeed_fsi_base_addr = base_addr; in test_fsi_setup()
62 if (base_addr == AST2600_OPB_FSI0_BASE_ADDR) { in test_fsi_setup()
72 } else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) { in test_fsi_setup()
H A Dnpcm7xx_watchdog_timer-test.c38 uint64_t base_addr; member
44 .base_addr = 0xf0008000
48 .base_addr = 0xf0009000
52 .base_addr = 0xf000a000
67 return qtest_readl(qts, wd->base_addr + WTCR_OFFSET); in watchdog_read_wtcr()
73 qtest_writel(qts, wd->base_addr + WTCR_OFFSET, value); in watchdog_write_wtcr()
/openbmc/qemu/tests/qtest/libqos/
H A Dsdhci-cmd.c74 void sdhci_cmd_regs(QTestState *qts, uint64_t base_addr, uint16_t blksize, in sdhci_cmd_regs() argument
78 qtest_writew(qts, base_addr + SDHC_BLKSIZE, blksize); in sdhci_cmd_regs()
79 qtest_writew(qts, base_addr + SDHC_BLKCNT, blkcnt); in sdhci_cmd_regs()
80 qtest_writel(qts, base_addr + SDHC_ARGUMENT, argument); in sdhci_cmd_regs()
81 qtest_writew(qts, base_addr + SDHC_TRNMOD, trnmod); in sdhci_cmd_regs()
82 qtest_writew(qts, base_addr + SDHC_CMDREG, cmdreg); in sdhci_cmd_regs()
85 ssize_t sdhci_read_cmd(QTestState *qts, uint64_t base_addr, char *msg, in sdhci_read_cmd() argument
88 sdhci_cmd_regs(qts, base_addr, count, 1, 0, in sdhci_read_cmd()
93 ssize_t bytes_read = read_fifo(qts, base_addr + SDHC_BDATA, msg, count); in sdhci_read_cmd()
95 sdhci_cmd_regs(qts, base_addr, 0, 0, 0, in sdhci_read_cmd()
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H A Dsdhci-cmd.h62 void sdhci_cmd_regs(QTestState *qts, uint64_t base_addr, uint16_t blksize,
67 ssize_t sdhci_read_cmd(QTestState *qts, uint64_t base_addr, char *msg,
71 void sdhci_write_cmd(QTestState *qts, uint64_t base_addr, const char *msg,
/openbmc/u-boot/include/
H A Dnetdev.h31 int calxedaxgmac_initialize(u32 id, ulong base_addr);
32 int cs8900_initialize(u8 dev_num, int base_addr);
35 int designware_initialize(ulong base_addr, u32 interface);
40 int ep93xx_eth_initialize(u8 dev_num, int base_addr);
42 int ethoc_initialize(u8 dev_num, int base_addr);
49 int ks8851_mll_initialize(u8 dev_num, int base_addr);
50 int lan91c96_initialize(u8 dev_num, int base_addr);
56 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
68 int smc91111_initialize(u8 dev_num, int base_addr);
69 int smc911x_initialize(u8 dev_num, int base_addr);
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/openbmc/u-boot/drivers/video/
H A Dmali_dp.c88 phys_addr_t base_addr; member
103 static int malidp_get_hwid(phys_addr_t base_addr) in malidp_get_hwid() argument
111 hwid = readl(base_addr + MALIDP_CORE_ID); in malidp_get_hwid()
115 hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID); in malidp_get_hwid()
163 writel(val, malidp->base_addr + malidp->modeset_regs_offset + in malidp_setup_timings()
167 writel(val, malidp->base_addr + malidp->modeset_regs_offset + in malidp_setup_timings()
171 writel(val, malidp->base_addr + malidp->modeset_regs_offset + in malidp_setup_timings()
175 writel(val, malidp->base_addr + malidp->modeset_regs_offset + in malidp_setup_timings()
178 writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset + in malidp_setup_timings()
206 writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset + in malidp_setup_layer()
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/openbmc/u-boot/arch/x86/lib/
H A Dmrccache.c45 ulong base_addr, end_addr; in mrccache_find_current() local
48 base_addr = entry->base + entry->offset; in mrccache_find_current()
49 end_addr = base_addr + entry->length; in mrccache_find_current()
53 for (id = 0, next = (struct mrc_data_container *)base_addr; in mrccache_find_current()
90 ulong base_addr, end_addr; in find_next_mrc_cache() local
92 base_addr = entry->base + entry->offset; in find_next_mrc_cache()
93 end_addr = base_addr + entry->length; in find_next_mrc_cache()
113 ulong base_addr; in mrccache_update() local
120 base_addr = entry->base + entry->offset; in mrccache_update()
146 cache = (struct mrc_data_container *)base_addr; in mrccache_update()
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/openbmc/u-boot/board/compulab/common/
H A Domap3_smc911x.c30 static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) in cl_omap3_smc911x_setup_net_chip_gmpc() argument
35 &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); in cl_omap3_smc911x_setup_net_chip_gmpc()
74 int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, in cl_omap3_smc911x_init() argument
79 cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr); in cl_omap3_smc911x_init()
86 ret = smc911x_initialize(id, base_addr); in cl_omap3_smc911x_init()
H A Dcommon.h27 int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
30 static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, in cl_omap3_smc911x_init() argument
/openbmc/qemu/hw/net/rocker/
H A Drocker_desc.c26 hwaddr base_addr; member
104 bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr) in desc_ring_set_base_addr() argument
106 if (base_addr & 0x7) { in desc_ring_set_base_addr()
108 ") not 8-byte aligned\n", ring->index, base_addr); in desc_ring_set_base_addr()
112 ring->base_addr = base_addr; in desc_ring_set_base_addr()
119 return ring->base_addr; in desc_ring_get_base_addr()
159 hwaddr addr = ring->base_addr + (sizeof(RockerDesc) * index); in desc_read()
170 hwaddr addr = ring->base_addr + (sizeof(RockerDesc) * index); in desc_write()
177 if (!ring->base_addr) { in desc_ring_base_addr_check()
355 ring->base_addr = 0; in desc_ring_reset()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xxx/
H A Dfsl_pamu.c231 u32 base_addr = CONFIG_SYS_PAMU_ADDR; in pamu_init() local
268 regs = (struct ccsr_pamu *)base_addr; in pamu_init()
284 base_addr += PAMU_OFFSET; in pamu_init()
293 u32 base_addr = CONFIG_SYS_PAMU_ADDR; in pamu_enable() local
295 setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, in pamu_enable()
298 base_addr += PAMU_OFFSET; in pamu_enable()
305 u32 base_addr = CONFIG_SYS_PAMU_ADDR; in pamu_reset() local
309 regs = (struct ccsr_pamu *)base_addr; in pamu_reset()
322 base_addr += PAMU_OFFSET; in pamu_reset()
329 u32 base_addr = CONFIG_SYS_PAMU_ADDR; in pamu_disable() local
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/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dpinmux_arria10.c14 fdt_addr_t base_addr; in do_pinctr_pin() local
19 base_addr = fdtdec_get_addr_size(blob, child, "reg", &size); in do_pinctr_pin()
20 if (base_addr != FDT_ADDR_T_NONE) { in do_pinctr_pin()
30 writel(value, base_addr + offset); in do_pinctr_pin()
/openbmc/qemu/hw/pci/
H A Dpcie_host.c80 e->base_addr = PCIE_BASE_ADDR_UNMAPPED; in pcie_host_init()
87 if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { in pcie_host_mmcfg_unmap()
89 e->base_addr = PCIE_BASE_ADDR_UNMAPPED; in pcie_host_mmcfg_unmap()
106 e->base_addr = addr; in pcie_host_mmcfg_map()
107 memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); in pcie_host_mmcfg_map()
/openbmc/u-boot/drivers/gpio/
H A Dvybrid_gpio.c110 fdt_addr_t base_addr; in vybrid_gpio_odata_to_platdata() local
112 base_addr = devfdt_get_addr(dev); in vybrid_gpio_odata_to_platdata()
113 if (base_addr == FDT_ADDR_T_NONE) in vybrid_gpio_odata_to_platdata()
116 plat->base = base_addr; in vybrid_gpio_odata_to_platdata()
H A Dintel_ich6_gpio.c112 plat->base_addr = gpiobase + offset; in gpio_ich6_ofdata_to_platdata()
128 bank->use_sel = plat->base_addr; in ich6_gpio_probe()
129 bank->io_sel = plat->base_addr + 4; in ich6_gpio_probe()
130 bank->lvl = plat->base_addr + 8; in ich6_gpio_probe()
/openbmc/u-boot/arch/x86/cpu/tangier/
H A Dpinmux.c82 mrfld_setup_families(void *base_addr, in mrfld_setup_families() argument
88 family->regs = base_addr + in mrfld_setup_families()
161 void *base_addr = syscon_get_first_range(X86_SYSCON_PINCONF); in tangier_pinctrl_probe() local
166 mrfld_setup_families(base_addr, mrfld_families, in tangier_pinctrl_probe()
/openbmc/qemu/tests/multiboot/
H A Dmmap.c45 entry->base_addr, in test_main()
46 entry->base_addr + entry->length, in test_main()
/openbmc/u-boot/board/samsung/common/
H A Dboard.c206 fdt_addr_t base_addr; in board_eth_init() local
221 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); in board_eth_init()
222 if (base_addr == FDT_ADDR_T_NONE) { in board_eth_init()
247 return smc911x_initialize(0, base_addr); in board_eth_init()
/openbmc/qemu/hw/intc/
H A Dallwinner-a10-pic.c67 return s->base_addr; in aw_a10_pic_read()
99 s->base_addr = value & ~0x3; in aw_a10_pic_write()
147 VMSTATE_UINT32(base_addr, AwA10PICState),
177 s->base_addr = 0; in aw_a10_pic_reset()
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dclock.h76 int enable_lcdif_clock(u32 base_addr, bool enable);
79 void mxs_set_lcdclk(u32 base_addr, u32 freq);
/openbmc/qemu/include/hw/acpi/
H A Dcpu.h53 CPUHotplugState *state, hwaddr base_addr);
66 build_madt_cpu_fn build_madt_cpu, hwaddr base_addr,

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