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Searched refs:assigned (Results 1 – 25 of 254) sorted by relevance

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/openbmc/u-boot/arch/arm/dts/
H A Dimx7ulp.dtsi210 assigned-clock-rates = <48000000>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
223 assigned-clock-rates = <48000000>;
233 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
234 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
235 assigned-clock-rates = <48000000>;
245 assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
[all …]
H A Dfsl-imx8dx.dtsi249 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
250 assigned-clock-rates = <24000000>;
265 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
266 assigned-clock-rates = <24000000>;
280 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
281 assigned-clock-rates = <24000000>;
296 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
297 assigned-clock-rates = <24000000>;
399 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
400 assigned-clock-rates = <80000000>;
[all …]
H A Dimx7s-warp.dts79 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
80 assigned-clock-rates = <884736000>;
220 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
222 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
223 assigned-clock-rates = <0>, <36864000>;
230 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
231 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
238 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
239 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
247 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
H A Dmt7629.dtsi96 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
97 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
187 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
188 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
200 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
201 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
213 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
214 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
261 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
263 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
H A Dmeson-gxl-mali.dtsi32 assigned-clocks = <&clkc CLKID_GP0_PLL>,
36 assigned-clock-parents = <0>, /* Do Nothing */
40 assigned-clock-rates = <744000000>,
H A Ddra7-evm-common.dtsi206 assigned-clocks = <&abe_dpll_sys_clk_mux>,
211 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
212 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
225 assigned-clocks = <&mcasp3_ahclkx_mux>;
226 assigned-clock-parents = <&atl_clkin2_ck>;
/openbmc/u-boot/doc/device-tree-bindings/remoteproc/
H A Dk3-rproc.txt28 - assigned-clocks: Should contain a phandle to clock node and an args
32 - assigned-clock-rates: One entry for each entry of assigned-clocks. This is
34 to be assigned.
45 assigned-clocks = <&k3_clks 202 0>;
46 assigned-clock-rates = <800000000>;
/openbmc/u-boot/configs/
H A Devb-rk3229_defconfig26 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Drock_defconfig31 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Drock960-rk3399_defconfig34 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dficus-rk3399_defconfig32 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Devb-rk3399_defconfig33 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dfirefly-rk3399_defconfig33 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dfennec-rk3288_defconfig38 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dpopmetal-rk3288_defconfig38 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Devb-rk3288_defconfig37 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dtinker-rk3288_defconfig39 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dphycore-rk3288_defconfig40 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dfirefly-rk3288_defconfig37 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dmiqi-rk3288_defconfig37 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dchromebit_mickey_defconfig40 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dvyasa-rk3288_defconfig37 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dchromebook_bob_defconfig47 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dchromebook_minnie_defconfig41 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…
H A Dchromebook_speedy_defconfig42 …"pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigne…

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