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Searched refs:ahb_reset1_cfg (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c264 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
274 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
353 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
354 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); in sunxi_dw_hdmi_probe()
H A Dsunxi_display.c106 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
142 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_shutdown()
448 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); in sunxi_composer_init()
530 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcdc_init()
863 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
865 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
H A Dsunxi_lcd.c49 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcd_enable()
H A Dsunxi_de2.c54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c61 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h91 u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ member
H A Dclock_sun8i_a83t.h121 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member
H A Dclock_sun6i.h159 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member
/openbmc/u-boot/drivers/net/
H A Dsun8i_emac.c661 setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); in sun8i_emac_board_setup()