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/openbmc/qemu/tests/bench/
H A Datomic64-bench.c14 uint64_t accesses; member
70 info->accesses++; in thread_func()
104 info->accesses = 0; in create_threads()
125 val += th_info[i].accesses; in pr_stats()
/openbmc/qemu/contrib/plugins/
H A Dcache.c79 uint64_t accesses; member
267 cache->accesses = 0; in cache_init()
412 l1_dcaches[cache_idx]->accesses++; in vcpu_mem_access()
426 l2_ucaches[cache_idx]->accesses++; in vcpu_mem_access()
447 l1_icaches[cache_idx]->accesses++; in vcpu_insn_exec()
461 l2_ucaches[cache_idx]->accesses++; in vcpu_insn_exec()
569 l1_imem_accesses += l1_icaches[i]->accesses; in sum_stats()
570 l1_dmem_accesses += l1_dcaches[i]->accesses; in sum_stats()
574 l2_mem_accesses += l2_ucaches[i]->accesses; in sum_stats()
623 append_stats_line(rep, dcache->accesses, dcache->misses, in log_stats()
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H A Dhwprofile.c134 GList *accesses = g_hash_table_get_values(rec->detail); in plugin_exit() local
135 GList *io_it = g_list_sort_with_data(accesses, sort_loc, NULL); in plugin_exit()
/openbmc/u-boot/doc/
H A DREADME.unaligned-memory-access.txt9 unaligned accesses, why you need to write code that doesn't cause them,
16 Unaligned memory accesses occur when you try to read N bytes of data starting
53 - Some architectures are able to perform unaligned memory accesses
55 - Some architectures raise processor exceptions when unaligned accesses
58 - Some architectures raise processor exceptions when unaligned accesses
66 memory accesses to happen, your code will not work correctly on certain
97 to pad structures so that accesses to fields are suitably aligned (assuming
130 lead to unaligned accesses when accessing fields that do not satisfy
177 Here is another example of some code that could cause unaligned accesses:
185 This code will cause unaligned accesses every time the data parameter points
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H A DREADME.fsl_iim28 Read operations are implemented as read accesses to the shadow registers,
42 Override operations are implemented as write accesses to the shadow
H A DREADME.mxc_ocotp31 Read operations are implemented as read accesses to the shadow registers,
45 Override operations are implemented as write accesses to the shadow
H A DREADME.displaying-bmps4 Some architectures cannot handle unaligned memory accesses, and an attempt to
H A DREADME.NDS3220 - Multiple aligned and unaligned memory accesses for memory copy and stack
H A DREADME.generic_usb_ohci60 PCI Controllers need to do byte swapping on register accesses, so they
/openbmc/qemu/docs/devel/
H A Dsecure-coding-practices.rst46 accesses and data read from guest memory must be validated. A typical example
76 may make nonsense accesses to device registers such as starting operations
80 device register accesses while asynchronous operations are in progress. A
84 request completes. Unexpected accesses must not cause memory corruption or
87 Invalid device register accesses can be reported with
111 The ``null-co`` block driver is designed for performance: its read accesses are
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/tinymembench/
H A Dtinymembench_git.bb2 peak bandwidth of sequential memory accesses and the latency of random memory \
3 accesses. Bandwidth is measured by running different assembly code for the \
/openbmc/openbmc/meta-openembedded/meta-oe/dynamic-layers/meta-python/recipes-bsp/rwmem/
H A Drwmem_1.2.bb5 In mmap mode rwmem accesses a file by memory mapping it. \
9 In i2c mode rwmem accesses an i2c peripheral by sending i2c messages to it."
/openbmc/qemu/docs/specs/
H A Dacpi_mem_hotplug.rst49 All following accesses to other registers in 0xa00-0xa17
83 - write accesses to memory hot-plug registers not documented above are ignored
84 - read accesses to memory hot-plug registers not documented above return
H A Dfsi.rst22 "engines" that drive accesses on buses internal and external to the POWER
33 driving CFAM engine accesses into the POWER chip. At the hardware level
34 FSI is a bit-based protocol supporting synchronous and DMA-driven accesses
45 into APB, so all accesses are indirect through the bridge.
H A Dacpi_cpu_hotplug.rst39 All accesses to registers described below, imply little-endian byte order.
43 - write accesses are ignored
44 - read accesses return all bits set to 0.
113 Selects active CPU device. All following accesses to other
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/libraw1394/
H A Dlibraw1394_2.1.2.bb1 SUMMARY = "base library for low-level IEEE 1394 accesses"
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A D8250.txt35 - reg-io-width : the size (in bytes) of the IO accesses that should be
37 accesses to the UART (e.g. TI davinci).
H A Dsnps-dw-apb-uart.txt24 - reg-io-width : the size (in bytes) of the IO accesses that should be
26 accesses are used.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/sdparm/
H A Dsdparm_1.12.bb2 DESCRIPTION = "The sdparm utility accesses and optionally modifies \
/openbmc/qemu/target/arm/tcg/
H A Dm-nocp.decode52 # FP system register accesses: these are a special case because accesses
/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A D0001-docs-Disable-manual-validation.patch7 accesses network and --nonet option also does not disable this,
/openbmc/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc33 * previous storage accesses to have been performed to memory (which
121 * cacheable accesses. TCG_BAR_SC is required to provide this
/openbmc/qemu/docs/system/devices/
H A Dcxl.rst27 - BAR mapped memory accesses used for registers and mailboxes.
106 * Configuration of HDM Decoders to route CXL Memory accesses with
135 the HDM decoders which route incoming memory accesses to the
167 | | | | memory accesses across HB0/HB1 | | | |
216 programmable HDM decoders to route memory accesses either to
225 CXL Type 3 1. HDM3 routes those interleaved accesses from
242 they will take the Host Physical Addresses of accesses and map
252 | | | | memory accesses across HB0/HB1 | | | |
/openbmc/openbmc/meta-security/recipes-mac/smack/
H A Dsmack_1.3.1.bb42 install -d ${D}${sysconfdir}/smack/accesses.d
/openbmc/u-boot/arch/arm/
H A DKconfig.debug56 bool "Use 32-bit accesses for 8250 UART"

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