| /openbmc/qemu/target/ppc/ |
| H A D | mmu-radix64.c | 115 static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_segi() argument
121 switch (access_type) { in ppc_radix64_raise_segi()
138 static inline const char *access_str(MMUAccessType access_type) in access_str() argument
140 return access_type == MMU_DATA_LOAD ? "reading" : in access_str()
141 (access_type == MMU_DATA_STORE ? "writing" : "execute"); in access_str()
144 static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_si() argument
151 __func__, access_str(access_type), in ppc_radix64_raise_si()
154 switch (access_type) { in ppc_radix64_raise_si()
175 static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_type, in ppc_radix64_raise_hsi() argument
184 env->error_code = access_type; in ppc_radix64_raise_hsi()
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| H A D | mmu-booke.c | 73 MMUAccessType access_type) in mmu40x_get_physical_address() argument
90 __func__, i, zsel, zpr, access_type, tlb->attr); in mmu40x_get_physical_address()
117 if (check_prot_access_type(*prot, access_type)) { in mmu40x_get_physical_address()
159 MMUAccessType access_type, int i) in mmubooke_check_tlb() argument
167 if ((access_type == MMU_INST_FETCH ? in mmubooke_check_tlb()
179 if (check_prot_access_type(*prot, access_type)) { in mmubooke_check_tlb()
185 return access_type == MMU_INST_FETCH ? -3 : -2; in mmubooke_check_tlb()
190 MMUAccessType access_type) in mmubooke_get_physical_address() argument
198 access_type, i); in mmubooke_get_physical_address()
266 static uint32_t mmubooke206_esr(int mmu_idx, MMUAccessType access_type) in mmubooke206_esr() argument
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| H A D | mmu-hash32.c | 52 MMUAccessType access_type, int *prot, in ppc_hash32_bat_lookup() argument
57 bool ifetch = access_type == MMU_INST_FETCH; in ppc_hash32_bat_lookup()
115 MMUAccessType access_type, in ppc_hash32_direct_store() argument
124 if (access_type == MMU_INST_FETCH) { in ppc_hash32_direct_store()
137 switch (guest_visible ? env->access_type : ACCESS_INT) { in ppc_hash32_direct_store()
151 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
171 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
186 if (check_prot_access_type(*prot, access_type)) { in ppc_hash32_direct_store()
195 if (access_type == MMU_DATA_STORE) { in ppc_hash32_direct_store()
294 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, in ppc_hash32_xlate() argument
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| H A D | mmu_common.c | 89 target_ulong eaddr, MMUAccessType access_type, in ppc6xx_tlb_check() argument
95 bool is_code = (access_type == MMU_INST_FETCH); in ppc6xx_tlb_check()
118 access_type == MMU_DATA_STORE ? 'S' : 'L', in ppc6xx_tlb_check()
119 access_type == MMU_INST_FETCH ? 'I' : 'D'); in ppc6xx_tlb_check()
136 if (check_prot_access_type(*prot, access_type)) { in ppc6xx_tlb_check()
153 if (access_type == MMU_DATA_STORE && ret == 0) { in ppc6xx_tlb_check()
191 target_ulong eaddr, MMUAccessType access_type, in get_bat_6xx_tlb() argument
197 bool ifetch = access_type == MMU_INST_FETCH; in get_bat_6xx_tlb()
226 if (check_prot_access_type(*prot, access_type)) { in get_bat_6xx_tlb()
264 MMUAccessType access_type, int type) in mmu6xx_get_physical_address() argument
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| H A D | user_only_helper.c | 26 MMUAccessType access_type, in ppc_cpu_record_sigsegv() argument
39 if (access_type == MMU_INST_FETCH) { in ppc_cpu_record_sigsegv()
45 if (access_type == MMU_DATA_STORE) { in ppc_cpu_record_sigsegv()
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| H A D | internal.h | 241 static inline int check_prot_access_type(int prot, MMUAccessType access_type) in check_prot_access_type() argument
243 return prot & (1 << access_type); in check_prot_access_type()
248 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
276 MMUAccessType access_type,
280 MMUAccessType access_type, int mmu_idx,
283 MMUAccessType access_type, int mmu_idx,
287 MMUAccessType access_type,
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| H A D | mmu-booke.h | 9 MMUAccessType access_type);
13 bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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| /openbmc/qemu/target/mips/system/ |
| H A D | physaddr.c | 79 MMUAccessType access_type, int mmu_idx, in get_seg_physical_address() argument
92 access_type); in get_seg_physical_address()
103 MMUAccessType access_type, int mmu_idx, in get_segctl_physical_address() argument
111 access_type, mmu_idx, am, eu, segmask, in get_segctl_physical_address()
117 MMUAccessType access_type, int mmu_idx) in get_physical_address() argument
142 real_address, access_type, in get_physical_address()
149 real_address, access_type); in get_physical_address()
158 real_address, access_type); in get_physical_address()
185 real_address, access_type, in get_physical_address()
199 real_address, access_type); in get_physical_address()
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | tlb_helper.c | 172 MMUAccessType access_type, in arm_deliver_fault() argument
187 bool is_vncr = (access_type != MMU_INST_FETCH) && in arm_deliver_fault()
201 access_type == MMU_INST_FETCH, in arm_deliver_fault()
204 access_type == MMU_DATA_STORE, fsc); in arm_deliver_fault()
245 if (access_type == MMU_INST_FETCH) { in arm_deliver_fault()
250 same_el, access_type == MMU_DATA_STORE, in arm_deliver_fault()
252 if (access_type == MMU_DATA_STORE in arm_deliver_fault()
267 MMUAccessType access_type, in arm_cpu_do_unaligned_access() argument
277 arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); in arm_cpu_do_unaligned_access()
306 MMUAccessType access_type, in arm_cpu_do_transaction_failed() argument
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
101 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
346 enum hws_access_type access_type = ACCESS_TYPE_UNICAST; in hws_ddr3_tip_init_controller() local
399 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
405 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
410 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
415 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
426 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
431 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
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| H A D | ddr3_training_bist.c | 13 enum hws_access_type access_type,
21 enum hws_access_type access_type, u32 if_num, in ddr3_tip_bist_activate() argument
34 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
39 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_CTRL_REG, in ddr3_tip_bist_activate()
44 ddr3_tip_load_pattern_to_odpg(0, access_type, 0, pattern, offset); in ddr3_tip_bist_activate()
46 …ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_SIZE_REG, pattern_addr_length, MASK_ALL_BITS… in ddr3_tip_bist_activate()
51 ddr3_tip_configure_odpg(0, access_type, 0, dir, in ddr3_tip_bist_activate()
56 ddr3_tip_if_write(0, access_type, 0, ODPG_DATA_BUFFER_OFFS_REG, offset, MASK_ALL_BITS); in ddr3_tip_bist_activate()
59 ddr3_tip_bist_operation(0, access_type, 0, BIST_STOP); in ddr3_tip_bist_activate()
61 ddr3_tip_bist_operation(0, access_type, 0, BIST_START); in ddr3_tip_bist_activate()
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| H A D | ddr3_training_ip_engine.c | 336 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training() argument
379 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
383 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
388 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
392 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
398 ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num, in ddr3_tip_ip_training()
406 (dev_num, access_type, interface_num, direction, in ddr3_tip_ip_training()
414 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
437 (dev_num, access_type, interface_num, in ddr3_tip_ip_training()
444 (dev_num, access_type, interface_num, OPCODE_REG0_REG(1), in ddr3_tip_ip_training()
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| /openbmc/qemu/include/accel/tcg/ |
| H A D | probe.h | 31 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
65 MMUAccessType access_type, int mmu_idx,
86 MMUAccessType access_type, int mmu_idx,
101 MMUAccessType access_type, int mmu_idx,
120 MMUAccessType access_type, int mmu_idx);
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| H A D | cpu-ops.h | 135 MMUAccessType access_type,
159 MMUAccessType access_type, uintptr_t ra);
213 MMUAccessType access_type, int mmu_idx,
223 MMUAccessType access_type, int mmu_idx,
237 unsigned size, MMUAccessType access_type,
245 MMUAccessType access_type,
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| /openbmc/qemu/target/i386/tcg/user/ |
| H A D | excp_helper.c | 25 MMUAccessType access_type, in x86_cpu_record_sigsegv() argument
39 env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT) in x86_cpu_record_sigsegv()
52 MMUAccessType access_type, uintptr_t ra) in x86_cpu_record_sigbus() argument
55 handle_unaligned_access(&cpu->env, addr, access_type, ra); in x86_cpu_record_sigbus()
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| /openbmc/qemu/target/i386/tcg/system/ |
| H A D | excp_helper.c | 36 MMUAccessType access_type; member
149 const MMUAccessType access_type = in->access_type; in mmu_translate() local
407 if ((pkr_prot & (1 << access_type)) == 0) { in mmu_translate()
413 if ((prot & (1 << access_type)) == 0) { in mmu_translate()
420 if (access_type == MMU_DATA_STORE) { in mmu_translate()
450 flags = probe_access_full_mmu(env, paddr, 0, access_type, in mmu_translate()
465 if ((prot & (1 << access_type)) == 0) { in mmu_translate()
495 assert(access_type != MMU_INST_FETCH); in mmu_translate()
504 switch (access_type) { in mmu_translate()
547 MMUAccessType access_type, int mmu_idx, in get_physical_address() argument
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| /openbmc/qemu/target/alpha/ |
| H A D | mem_helper.c | 42 MMUAccessType access_type, uintptr_t retaddr) in alpha_cpu_record_sigbus() argument
48 MMUAccessType access_type, in alpha_cpu_do_unaligned_access() argument
61 MMUAccessType access_type, in alpha_cpu_do_transaction_failed() argument
68 env->trap_arg1 = access_type == MMU_DATA_STORE ? 1 : 0; in alpha_cpu_do_transaction_failed()
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| /openbmc/qemu/target/microblaze/ |
| H A D | helper.c | 61 MMUAccessType access_type, in mb_cpu_do_unaligned_access() argument
75 MMUAccessType access_type) in mb_cpu_access_is_secure() argument
77 if (access_type == MMU_INST_FETCH) { in mb_cpu_access_is_secure()
85 MMUAccessType access_type, int mmu_idx, in mb_cpu_tlb_fill() argument
95 attrs.secure = mb_cpu_access_is_secure(cpu, access_type); in mb_cpu_tlb_fill()
106 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); in mb_cpu_tlb_fill()
129 env->esr = access_type == MMU_INST_FETCH ? 17 : 16; in mb_cpu_tlb_fill()
130 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill()
133 env->esr = access_type == MMU_INST_FETCH ? 19 : 18; in mb_cpu_tlb_fill()
134 env->esr |= (access_type == MMU_DATA_STORE) << 10; in mb_cpu_tlb_fill()
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| /openbmc/qemu/target/m68k/ |
| H A D | helper.c | 684 int access_type) in check_TTR() argument
697 if ((access_type & ACCESS_SUPER) != 0) { in check_TTR()
703 if ((access_type & ACCESS_SUPER) == 0) { in check_TTR()
732 int access_type, target_ulong *page_size) in get_physical_address() argument
738 bool debug = access_type & ACCESS_DEBUG; in get_physical_address()
745 if (check_TTR(env->mmu.TTR(access_type, i), in get_physical_address()
746 prot, address, access_type)) { in get_physical_address()
747 if (access_type & ACCESS_PTEST) { in get_physical_address()
759 if (access_type & ACCESS_CODE) { in get_physical_address()
762 if (access_type & ACCESS_SUPER) { in get_physical_address()
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | helper-tcg.h | 74 MMUAccessType access_type,
78 MMUAccessType access_type,
81 MMUAccessType access_type, uintptr_t ra);
84 MMUAccessType access_type, int mmu_idx,
87 MMUAccessType access_type,
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | tcg-internal.h | 24 MMUAccessType access_type, int mmu_idx,
58 MMUAccessType access_type, uintptr_t retaddr);
61 MMUAccessType access_type,
67 MMUAccessType access_type, int mmu_idx,
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| /openbmc/qemu/target/loongarch/tcg/ |
| H A D | tcg_loongarch.h | 14 MMUAccessType access_type, int mmu_idx,
19 MMUAccessType access_type, int mmu_idx);
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| /openbmc/qemu/accel/tcg/ |
| H A D | cputlb.c | 108 MMUAccessType access_type) in tlb_read_idx() argument
118 const uintptr_t *ptr = &entry->addr_idx[access_type]; in tlb_read_idx()
1001 MMUAccessType access_type, bool enable) in tlb_set_compare() argument
1013 ent->addr_idx[access_type] = address; in tlb_set_compare()
1014 full->slow_flags[access_type] = flags; in tlb_set_compare()
1266 MMUAccessType access_type, in cpu_unaligned_access() argument
1269 cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, in cpu_unaligned_access()
1292 unsigned size, MMUAccessType access_type, int mmu_idx, in io_failed() argument
1300 access_type, mmu_idx, in io_failed()
1308 MMUAccessType access_type, vaddr page) in victim_tlb_hit() argument
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| /openbmc/u-boot/drivers/pci/ |
| H A D | pci_gt64120.c | 44 unsigned char access_type, pci_dev_t bdf, in gt_config_access() argument
59 if (access_type == PCI_ACCESS_WRITE) in gt_config_access()
74 if (access_type == PCI_ACCESS_WRITE) { in gt_config_access()
108 if (access_type == PCI_ACCESS_READ) in gt_config_access()
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| /openbmc/qemu/target/arm/ |
| H A D | ptw.c | 77 MMUAccessType access_type, MemOp memop,
83 MMUAccessType access_type, MemOp memop,
982 uint32_t address, MMUAccessType access_type, in get_phys_addr_v5() argument
1092 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_v5()
1106 uint32_t address, MMUAccessType access_type, in get_phys_addr_v6() argument
1246 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_v6()
1653 MMUAccessType access_type, MemOp memop, in get_phys_addr_lpae() argument
1681 access_type != MMU_INST_FETCH, in get_phys_addr_lpae()
1948 && access_type == MMU_DATA_STORE) { in get_phys_addr_lpae()
2126 if (!(result->f.prot & (1 << access_type))) { in get_phys_addr_lpae()
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