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Searched refs:accel (Results 1 – 25 of 59) sorted by relevance

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/openbmc/qemu/accel/
H A Daccel-system.c38 int accel_init_machine(AccelState *accel, MachineState *ms) in accel_init_machine() argument
40 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_init_machine()
42 ms->accelerator = accel; in accel_init_machine()
44 ret = acc->init_machine(accel, ms); in accel_init_machine()
48 object_unref(OBJECT(accel)); in accel_init_machine()
62 AccelState *accel = ms->accelerator; in accel_setup_post() local
63 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_setup_post()
65 acc->setup_post(accel); in accel_setup_post()
71 AccelState *accel = ms->accelerator; in accel_pre_resume() local
72 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_pre_resume()
[all …]
H A Daccel-user.c21 static AccelState *accel; in current_accel() local
23 if (!accel) { in current_accel()
27 accel = ACCEL(object_new_with_class(OBJECT_CLASS(ac))); in current_accel()
29 return accel; in current_accel()
H A Daccel-common.c95 AccelState *accel = current_accel(); in accel_cpu_common_realize() local
96 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_cpu_common_realize()
115 AccelState *accel = current_accel(); in accel_cpu_common_unrealize() local
116 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_cpu_common_unrealize()
126 AccelState *accel = current_accel(); in accel_supported_gdbstub_sstep_flags() local
127 AccelClass *acc = ACCEL_GET_CLASS(accel); in accel_supported_gdbstub_sstep_flags()
129 return acc->gdbstub_supported_sstep_flags(accel); in accel_supported_gdbstub_sstep_flags()
H A Daccel-qmp.c19 AccelState *accel = current_accel(); in qmp_x_accel_stats() local
20 AccelClass *acc = ACCEL_GET_CLASS(accel); in qmp_x_accel_stats()
24 acc->get_stats(accel, buf); in qmp_x_accel_stats()
/openbmc/qemu/target/i386/hvf/
H A Dx86.c64 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_read_segment_descriptor()
65 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_read_segment_descriptor()
67 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_read_segment_descriptor()
68 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_read_segment_descriptor()
87 base = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_BASE); in x86_write_segment_descriptor()
88 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_GDTR_LIMIT); in x86_write_segment_descriptor()
90 base = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_BASE); in x86_write_segment_descriptor()
91 limit = rvmcs(cpu->accel->fd, VMCS_GUEST_LDTR_LIMIT); in x86_write_segment_descriptor()
105 target_ulong base = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_BASE); in x86_read_call_gate()
106 uint32_t limit = rvmcs(cpu->accel->fd, VMCS_GUEST_IDTR_LIMIT); in x86_read_call_gate()
[all …]
H A Dx86_descr.c50 return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_limit()
55 return (uint32_t)rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); in vmx_read_segment_ar()
60 return rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); in vmx_read_segment_base()
66 sel.sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); in vmx_read_segment_selector()
72 wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); in vmx_write_segment_selector()
77 desc->sel = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector); in vmx_read_segment_descriptor()
78 desc->base = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].base); in vmx_read_segment_descriptor()
79 desc->limit = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].limit); in vmx_read_segment_descriptor()
80 desc->ar = rvmcs(cpu->accel->fd, vmx_segment_fields[seg].ar_bytes); in vmx_read_segment_descriptor()
87 wvmcs(cpu->accel->fd, sf->base, desc->base); in vmx_write_segment_descriptor()
[all …]
H A Dvmx.h183 wreg(cpu->accel->fd, HV_X86_RIP, rip); in macvm_set_rip()
187 val = rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in macvm_set_rip()
191 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, in macvm_set_rip()
203 uint32_t gi = (uint32_t) rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in vmx_clear_nmi_blocking()
205 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); in vmx_clear_nmi_blocking()
214 uint32_t gi = (uint32_t)rvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY); in vmx_set_nmi_blocking()
216 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, gi); in vmx_set_nmi_blocking()
222 val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); in vmx_set_nmi_window_exiting()
223 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | in vmx_set_nmi_window_exiting()
232 val = rvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS); in vmx_clear_nmi_window_exiting()
[all …]
H A Dx86_task.c64 wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); in load_state_from_tss32()
113 uint64_t rip = rreg(cpu->accel->fd, HV_X86_RIP); in vmx_handle_task_switch()
117 int ins_len = rvmcs(cpu->accel->fd, VMCS_EXIT_INSTRUCTION_LENGTH); in vmx_handle_task_switch()
176 macvm_set_cr0(cpu->accel->fd, rvmcs(cpu->accel->fd, VMCS_GUEST_CR0) | in vmx_handle_task_switch()
183 hv_vcpu_invalidate_tlb(cpu->accel->fd); in vmx_handle_task_switch()
H A Dx86_mmu.c130 uint32_t cr0 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR0); in test_pt_entry()
184 target_ulong cr3 = rvmcs(cpu->accel->fd, VMCS_GUEST_CR3); in walk_gpt()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/om-gta01/
H A Dfb.modes7 accel false
14 accel false
21 accel false
28 accel false
/openbmc/qemu/accel/tcg/
H A Dmeson.build34 'tcg-accel-ops.c',
35 'tcg-accel-ops-icount.c',
36 'tcg-accel-ops-mttcg.c',
37 'tcg-accel-ops-rr.c',
H A Dtcg-stats.c40 static void dump_accel_info(AccelState *accel, GString *buf) in dump_accel_info() argument
42 bool one_insn_per_tb = object_property_get_bool(OBJECT(accel), in dump_accel_info()
209 void tcg_get_stats(AccelState *accel, GString *buf) in tcg_get_stats() argument
211 dump_accel_info(accel, buf); in tcg_get_stats()
/openbmc/qemu/docs/devel/migration/
H A Dqpl-compression.rst22 | MultiFD Thread | |accel-config tool |
85 The ``accel-config`` tool is used to enable ``IAA`` devices and configure
90 For ``accel-config`` installation, please refer to `accel-config installation
97 #accel-config config-engine iax1/engine1.0 -g 0
98 #accel-config config-engine iax1/engine1.1 -g 0
99 #accel-config config-engine iax1/engine1.2 -g 0
100 #accel-config config-engine iax1/engine1.3 -g 0
101 #accel-config config-engine iax1/engine1.4 -g 0
102 #accel-config config-engine iax1/engine1.5 -g 0
103 #accel-config config-engine iax1/engine1.6 -g 0
[all …]
/openbmc/qemu/system/
H A Drunstate-hmp-cmds.c46 AccelState *accel = current_accel(); in hmp_one_insn_per_tb() local
49 if (!object_property_find(OBJECT(accel), "one-insn-per-tb")) { in hmp_one_insn_per_tb()
64 object_property_set_bool(OBJECT(accel), "one-insn-per-tb", in hmp_one_insn_per_tb()
/openbmc/qemu/tests/functional/
H A Dtest_aarch64_smmu.py
/openbmc/qemu/target/i386/whpx/
H A Dmeson.build4 'whpx-accel-ops.c',
/openbmc/qemu/accel/hvf/
H A Dmeson.build4 'hvf-accel-ops.c',
H A Dtrace-events5 # hvf-accel-ops.c
/openbmc/qemu/target/i386/nvmm/
H A Dmeson.build4 'nvmm-accel-ops.c',
/openbmc/qemu/accel/kvm/
H A Dmeson.build4 'kvm-accel-ops.c',
/openbmc/qemu/
H A DKconfig3 source accel/Kconfig
/openbmc/qemu/include/accel/tcg/
H A Diommu.h11 #error Cannot include accel/tcg/iommu.h from user emulation
/openbmc/qemu/include/accel/
H A Daccel-ops.h34 bool (*has_memory)(AccelState *accel, AddressSpace *as,
/openbmc/qemu/include/qemu/
H A Daccel.h50 int accel_init_machine(AccelState *accel, MachineState *ms);
/openbmc/qemu/docs/specs/
H A Driscv-aia.rst31 chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split",
38 .. list-table:: How AIA and accel options changes controller emulation

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