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Searched refs:a32 (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a32.h107 TCGv_i32 a32, int index, MemOp opc);
109 TCGv_i32 a32, int index, MemOp opc);
111 TCGv_i32 a32, int index, MemOp opc);
113 TCGv_i32 a32, int index, MemOp opc);
114 void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
116 void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
118 void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
120 void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
125 TCGv_i32 a32, int index) \
127 gen_aa32_ld_i32(s, val, a32, index, OPC); \
[all …]
H A Dmeson.build16 decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'),
17 decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'),
H A Da32-uncond.decode22 # All of those that have a COND field in insn[31:28] are in a32.decode
H A Dtranslate.c24 #include "translate-a32.h"
911 static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) in gen_aa32_addr()
914 tcg_gen_extu_i32_tl(addr, a32); in gen_aa32_addr()
928 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i32()
930 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i32()
935 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_st_internal_i32()
937 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_st_internal_i32()
942 TCGv_i32 a32, int index, MemOp opc) in gen_aa32_ld_internal_i64()
944 TCGv addr = gen_aa32_addr(s, a32, opc); in gen_aa32_ld_internal_i64()
955 TCGv_i32 a32, in in gen_aa32_st_internal_i64()
910 gen_aa32_addr(DisasContext * s,TCGv_i32 a32,MemOp op) gen_aa32_addr() argument
927 gen_aa32_ld_internal_i32(DisasContext * s,TCGv_i32 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_ld_internal_i32() argument
934 gen_aa32_st_internal_i32(DisasContext * s,TCGv_i32 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_st_internal_i32() argument
941 gen_aa32_ld_internal_i64(DisasContext * s,TCGv_i64 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_ld_internal_i64() argument
954 gen_aa32_st_internal_i64(DisasContext * s,TCGv_i64 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_st_internal_i64() argument
968 gen_aa32_ld_i32(DisasContext * s,TCGv_i32 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_ld_i32() argument
974 gen_aa32_st_i32(DisasContext * s,TCGv_i32 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_st_i32() argument
980 gen_aa32_ld_i64(DisasContext * s,TCGv_i64 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_ld_i64() argument
986 gen_aa32_st_i64(DisasContext * s,TCGv_i64 val,TCGv_i32 a32,int index,MemOp opc) gen_aa32_st_i64() argument
[all...]
H A Da32.decode22 # All insns that have 0xf in insn[31:28] are in a32-uncond.decode.
/openbmc/qemu/tests/tcg/s390x/
H A Dadd-logical-with-carry.c44 unsigned int a32 = a, b32 = b, c32 = c; in test32rm() local
50 : [a] "+&r" (a32), [cc] "+&r" (*cc) in test32rm()
55 return (int)a32; in test32rm()
62 unsigned int a32 = a, b32 = b, c32 = c; in test32mr() local
68 : [a] "+&r" (a32), [c] "+&r" (c32), [cc] "+&r" (*cc) in test32mr()
/openbmc/qemu/tests/tcg/arm/
H A DMakefile.target32 ARM_TESTS += pcalign-a32
33 pcalign-a32: CFLAGS+=-marm
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8a/
H A Dtune-cortexa32.inc4 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa32', ' -mcpu=cortex-a32', '', d)}"
/openbmc/u-boot/arch/x86/cpu/
H A Dstart16.S16 #define a32 .byte 0x67; macro
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/ltrace/ltrace/
H A D0001-Add-support-for-mips64-n32-n64.patch349 - uint32_t a32 = (uint32_t) addr;
350 - if (ptrace(PTRACE_POKETEXT, proc->pid, a32, v32) < 0) {