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Searched refs:_pcwbits (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-apmixed.c23 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
30 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
36 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
38 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt7981-apmixed.c25 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
32 .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
40 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt8516-apmixedsys.c23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
34 .pcwbits = _pcwbits, \
43 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
46 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt8167-apmixedsys.c22 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
33 .pcwbits = _pcwbits, \
42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
45 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt7622-apmixedsys.c20 #define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\ argument
31 .pcwbits = _pcwbits, \
41 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
44 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
H A Dclk-mt2712-apmixedsys.c21 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
33 .pcwbits = _pcwbits, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
48 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
H A Dclk-mt8365-apmixedsys.c19 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
32 .pcwbits = _pcwbits, \
45 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
50 _pcwbits, _pd_reg, _pd_shift, \
H A Dclk-mt8183-apmixedsys.c55 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
68 .pcwbits = _pcwbits, \
82 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
87 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
H A Dclk-mt8192-apmixedsys.c36 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
49 .pcwbits = _pcwbits, \
64 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
68 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
H A Dclk-mt8173-apmixedsys.c24 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
35 .pcwbits = _pcwbits, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… argument
29 .pcwbits = _pcwbits, \
H A Dclk-mt8188-apmixedsys.c33 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
46 .pcwbits = _pcwbits, \
H A Dclk-mt7629.c23 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
34 .pcwbits = _pcwbits, \
44 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
47 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt8186-apmixedsys.c20 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
32 .pcwbits = _pcwbits, \
H A Dclk-mt6797.c599 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
610 .pcwbits = _pcwbits, \
619 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
622 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
H A Dclk-mt6795-apmixedsys.c26 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
36 .pcwbits = _pcwbits, \
H A Dclk-mt8195-apmixedsys.c34 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ argument
47 .pcwbits = _pcwbits, \
H A Dclk-mt6779.c1146 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
1159 .pcwbits = _pcwbits, \
1173 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \ argument
1178 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
H A Dclk-mt6765.c671 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
683 .pcwbits = _pcwbits, \
695 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
700 _pcwbits, _pcwibits, _pd_reg, _pd_shift, \
H A Dclk-mt2701.c921 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
931 .pcwbits = _pcwbits, \
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
40 .pcwbits = _pcwbits, \
H A Dclk-mt7623.c27 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ argument
36 .pcwbits = _pcwbits, \