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/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.h32 #define JH71X0_GATE(_idx, _name, _flags, _parent) \ argument
33 [_idx] = { \
40 #define JH71X0__DIV(_idx, _name, _max, _parent) \ argument
41 [_idx] = { \
48 #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ argument
49 [_idx] = { \
56 #define JH71X0_FDIV(_idx, _name, _parent) \ argument
57 [_idx] = { \
64 #define JH71X0__MUX(_idx, _name, _nparents, ...) \ argument
65 [_idx] = { \
[all …]
H A Dclk-starfive-jh7110-pll.c111 #define _JH7110_PLL(_idx, _name, _presets) \ argument
112 [_idx] = { \
117 .pd = JH7110_PLL##_idx##_PD_OFFSET, \
118 .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \
119 .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
123 .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \
124 .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \
125 .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \
128 .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h239 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
240 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
241 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
242 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) argument
243 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) argument
244 #define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16)) argument
245 #define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16)) argument
/openbmc/linux/include/linux/
H A Dgeneric-radix-tree.h120 #define __genradix_idx_to_offset(_radix, _idx) \ argument
121 __idx_to_offset(_idx, __genradix_obj_size(_radix))
132 #define genradix_ptr(_radix, _idx) \ argument
135 __genradix_idx_to_offset(_radix, _idx)))
148 #define genradix_ptr_alloc(_radix, _idx, _gfp) \ argument
151 __genradix_idx_to_offset(_radix, _idx), \
164 #define genradix_iter_init(_radix, _idx) \ argument
166 .pos = (_idx), \
167 .offset = __genradix_idx_to_offset((_radix), (_idx)),\
H A Dlinear_range.h37 #define LINEAR_RANGE_IDX(_idx, _min, _min_sel, _max_sel, _step) \ argument
38 [_idx] = LINEAR_RANGE(_min, _min_sel, _max_sel, _step)
/openbmc/linux/tools/perf/tests/
H A Dfdarray.c102 #define FDA_CHECK(_idx, _fd, _revents) \ in test__fdarray__add() argument
103 if (fda->entries[_idx].fd != _fd) { \ in test__fdarray__add()
105 __LINE__, _idx, fda->entries[1].fd, _fd); \ in test__fdarray__add()
108 if (fda->entries[_idx].events != (_revents)) { \ in test__fdarray__add()
110 __LINE__, _idx, fda->entries[_idx].fd, _revents); \ in test__fdarray__add()
114 #define FDA_ADD(_idx, _fd, _revents, _nr) \ in test__fdarray__add() argument
125 FDA_CHECK(_idx, _fd, _revents) in test__fdarray__add()
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h69 #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \ argument
74 .idx = (_idx), \
83 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ argument
87 .idx = (_idx), \
95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
99 .idx = (_idx), \
H A Dclk-uniphier-mio.c21 #define UNIPHIER_MIO_CLK_SD(_idx, ch) \ argument
61 UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
/openbmc/linux/drivers/usb/gadget/udc/
H A Dpxa27x_udc.h263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ argument
266 .name = "ep" #_idx, \
267 .idx = _idx, .enabled = 0, \
272 #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ argument
273 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
275 #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ argument
276 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
278 #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ argument
279 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
/openbmc/linux/include/rdma/
H A Duverbs_ioctl.h954 #define uverbs_get_const_signed(_to, _attrs_bundle, _idx) \ argument
958 _uverbs_get_const_signed(&_val, _attrs_bundle, _idx, \
965 #define uverbs_get_const_unsigned(_to, _attrs_bundle, _idx) \ argument
969 _uverbs_get_const_unsigned(&_val, _attrs_bundle, _idx, \
975 #define uverbs_get_const_default_signed(_to, _attrs_bundle, _idx, _default) \ argument
980 _uverbs_get_const_signed(&_val, _attrs_bundle, _idx, \
987 #define uverbs_get_const_default_unsigned(_to, _attrs_bundle, _idx, _default) \ argument
992 _uverbs_get_const_unsigned(&_val, _attrs_bundle, _idx, \
998 #define uverbs_get_const(_to, _attrs_bundle, _idx) \ argument
1000 uverbs_get_const_signed(_to, _attrs_bundle, _idx) : \
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h592 #define MT_SKEY_0(_bss, _idx) \ argument
593 (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32)
594 #define MT_SKEY_1(_bss, _idx) \ argument
595 (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32)
596 #define MT_SKEY(_bss, _idx) \ argument
597 ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
608 #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1))) argument
H A Dinit.c465 #define CHAN2G(_idx, _freq) { \ argument
468 .hw_value = (_idx), \
489 #define CCK_RATE(_idx, _rate) { \ argument
492 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
493 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
496 #define OFDM_RATE(_idx, _rate) { \ argument
498 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
499 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h668 #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32) argument
669 #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32) argument
670 #define MT_SKEY(_bss, _idx) (((_bss) & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) argument
678 #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * ((_bss) & 1))) argument
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dcommon-init.c21 #define CHAN2G(_freq, _idx) { \ argument
24 .hw_value = (_idx), \
28 #define CHAN5G(_freq, _idx) { \ argument
31 .hw_value = (_idx), \
/openbmc/linux/drivers/clk/nxp/
H A Dclk-lpc32xx.c189 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ argument
190 [CLK_PREFIX(_idx)] = { \
1083 #define LPC32XX_DEFINE_FIXED(_idx, _rate) \ argument
1084 [CLK_PREFIX(_idx)] = { \
1093 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \ argument
1094 [CLK_PREFIX(_idx)] = { \
1109 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1110 [CLK_PREFIX(_idx)] = { \
1130 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
1131 [CLK_PREFIX(_idx)] = { \
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c136 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
143 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
157 _parents##_idx, 0, _lock)
163 _parents##_idx, 0, NULL)
170 _clk_id, _parents##_idx, 0, NULL)
177 _clk_id, _parents##_idx, flags, NULL)
184 _clk_id, _parents##_idx, 0, NULL)
191 _parents##_idx, 0, NULL)
198 _parents##_idx, 0, NULL)
[all …]
/openbmc/linux/drivers/perf/
H A Dapple_m1_cpu_pmu.c180 #define PMU_READ_COUNTER(_idx) \ argument
181 case _idx: return read_sysreg_s(SYS_IMP_APL_PMC## _idx ##_EL1)
183 #define PMU_WRITE_COUNTER(_val, _idx) \ argument
184 case _idx: \
185 write_sysreg_s(_val, SYS_IMP_APL_PMC## _idx ##_EL1); \
/openbmc/linux/include/linux/gpio/
H A Dmachine.h89 #define GPIO_LOOKUP_IDX(_key, _chip_hwnum, _con_id, _idx, _flags) \ argument
94 .idx = _idx, \
/openbmc/linux/drivers/iio/adc/
H A Dmt6360-adc.c227 #define MT6360_ADC_CHAN(_idx, _type) { \ argument
229 .channel = MT6360_CHAN_##_idx, \
230 .scan_index = MT6360_CHAN_##_idx, \
231 .datasheet_name = #_idx, \
H A Dmt6370-adc.c262 #define MT6370_ADC_CHAN(_idx, _type, _addr, _extra_info) { \ argument
264 .channel = MT6370_CHAN_##_idx, \
266 .scan_index = MT6370_CHAN_##_idx, \
/openbmc/linux/include/xen/interface/io/
H A Dring.h193 #define RING_GET_REQUEST(_r, _idx) \ argument
194 (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].req))
196 #define RING_GET_RESPONSE(_r, _idx) \ argument
197 (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].rsp))
/openbmc/linux/drivers/regulator/
H A Dmax77826-regulator.c135 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
146 .enable_mask = BIT(_idx * 2 + 1), \
147 .vsel_reg = MAX77826_REG_BUCK_VOUT + _idx * 2, \
/openbmc/qemu/include/hw/xen/interface/io/
H A Dring.h232 #define RING_GET_REQUEST(_r, _idx) \ argument
233 (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].req))
235 #define RING_GET_RESPONSE(_r, _idx) \ argument
236 (&((_r)->sring->ring[((_idx) & (RING_SIZE(_r) - 1))].rsp))
/openbmc/linux/net/mac80211/
H A Drc80211_minstrel_ht.h65 #define MI_RATE(_group, _idx) \ argument
67 FIELD_PREP(MI_RATE_IDX_MASK, _idx))
/openbmc/linux/drivers/clk/renesas/
H A Dr9a06g032-clocks.c162 #define D_GATE(_idx, _n, _src, ...) { \ argument
164 .index = R9A06G032_##_idx, \
169 #define D_MODULE(_idx, _n, _src, ...) { \ argument
171 .index = R9A06G032_##_idx, \
177 #define D_ROOT(_idx, _n, _mul, _div) { \ argument
179 .index = R9A06G032_##_idx, \
184 #define D_FFC(_idx, _n, _src, _div) { \ argument
186 .index = R9A06G032_##_idx, \
192 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \ argument
194 .index = R9A06G032_##_idx, \
[all …]

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