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Searched refs:__REG2 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dimx-regs.h16 # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) macro
19 # define __REG2(x,y) ((x)+(y)) macro
111 #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
112 #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
113 #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
114 #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
115 #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
116 #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
117 #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
118 #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
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/openbmc/linux/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c27 #define PGSR(x) __REG2(0x40F00020, (x) << 2)
28 #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
33 #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
34 #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
35 #define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
36 #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
H A Dpxa27x-udc.h105 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
152 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
178 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
206 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
H A Dpxa-regs.h39 # define __REG2(x,y) \ macro
H A Dpxa2xx-regs.h40 #define PCMD(x) __REG2(0x40F00080, (x)<<2)
/openbmc/linux/arch/xtensa/include/asm/
H A Dcoprocessor.h106 #define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__) macro