Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (Results 1 – 1 of 1) sorted by relevance
199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16) macro229 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK; in pcie_phy_enable()