Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (Results 1 – 1 of 1) sorted by relevance
193 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12) macro246 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK; in pcie_phy_enable()