Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL (Results 1 – 1 of 1) sorted by relevance
194 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12) macro248 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2); in pcie_phy_enable()